/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl20240411/quine20240404.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity quine20240404 is
port (
    x3, x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture behaviour of quine20240404 is
begin
    y <=    (x3 and not x2 and not x1) or
            (not x3 and x2) or
            (x2 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20240404testbench is
port (
    y: out std_logic
);
end;

architecture behaviour of quine20240404testbench is
    component quine20240404
    port (
        x3, x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
    signal x3, x2, x1, x0: std_logic;
begin
    q: quine20240404 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);