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0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
13 1 1 0 1 1
15 1 1 1 1 1
Gruppe 1:
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
5 0 1 0 1 1
6 0 1 1 0 1
9 1 0 0 1 1
Gruppe 3:
7 0 1 1 1 1
13 1 1 0 1 1
Gruppe 4:
15 1 1 1 1 1
4:5 0 1 0 -
4:6 0 1 - 0
8:9 1 0 0 -
5:7 0 1 - 1
5:13 - 1 0 1
6:7 0 1 1 -
9:13 1 - 0 1
7:15 - 1 1 1
13:15 1 1 - 1
4:5 0 1 0 -
6:7 0 1 1 -
8:9 1 0 0 -
4:6 0 1 - 0
5:7 0 1 - 1
13:15 1 1 - 1
9:13 1 - 0 1
5:13 - 1 0 1
7:15 - 1 1 1
Gruppe 1:
8:9 1 0 0 -
4:5 0 1 0 -
Gruppe 2:
6:7 0 1 1 -
Gruppe 1:
4:6 0 1 - 0
Gruppe 2:
5:7 0 1 - 1
Gruppe 3:
13:15 1 1 - 1
Gruppe 2:
9:13 1 - 0 1
Gruppe 2:
5:13 - 1 0 1
Gruppe 3:
7:15 - 1 1 1
Gruppe 1:
8:9 1 0 0 -
4:5 0 1 0 -
Gruppe 2:
6:7 0 1 1 -
4:5:6:7 0 1 - -
Gruppe 1:
4:6 0 1 - 0
Gruppe 2:
5:7 0 1 - 1
Gruppe 3:
13:15 1 1 - 1
4:6:5:7 0 1 - -
5:7:13:15 - 1 - 1
Gruppe 2:
9:13 1 - 0 1
9:13 1 - 0 1
Gruppe 2:
5:13 - 1 0 1
Gruppe 3:
7:15 - 1 1 1
5:13:7::15 - 1 - 1
8:9 1 0 0 -
4:5:6:7 0 1 - -
4:6:5:7 0 1 - -
5:7:13:15 - 1 - 1
9:13 1 - 0 1
5:13:7::15 - 1 - 1
8:9 1 0 0 -
4:5:6:7 0 1 - -
5:7:13:15 - 1 - 1
9:13 1 - 0 1
4 5 6 7 8 9 13 15
8:9 * *
4:5:6:7 * * * *
5:7:13:15 * * * *
9:13 * *
4 5 6 7 8 9 13 15
8:9 * * p
4:5:6:7 * * * * p
5:7:13:15 * * * * p
9:13 * *
4 5 6 7 8 9 13 15
8:9 * * p
4:5:6:7 * * * * p
5:7:13:15 * * * * p
8:9 1 0 0 -
4:5:6:7 0 1 - -
5:7:13:15 - 1 - 1
y <= (x3 and not x2 and not x1) or
(not x3 and x2) or
(x2 and x0);
y <= not (
(not x3 or x2 or x1) and
(x3 or not x2) and
(not x2 or not x0)
);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240404 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240404 is
begin
y <= (x3 and not x2 and not x1) or
(not x3 and x2) or
(x2 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240404testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240404testbench is
component quine20240404
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240404 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);