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0:1:2:3 * * * *
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0 1 2 3 4 5 7 8 9 11 12 13 15
0:1:2:3 * * * * p
0:8:1:9:4:12:5:13 * * * * * * * p
1:5:3:7:9:11:13:15 * * * * * * * * p
y <= (not x3 and not x2) or
(not x1) or
(x0);
y <= (x3 or x2) and
(x1) and
(not x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240410 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240410 is
begin
y <= (not x3 and not x2) or
(not x1) or
(x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240410testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240410testbench is
component quine20240410
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240410 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);