/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/old-cs-2-01/vhdl-2021-07-16/myfirst00001.vhdl

entity verhalte of multiplexer is
begin
(
    signal a3, a2, a1, a0: bit;
    signal b3, b2, b1, b0: bit;
    signal s: bit;
    signal y3, y2, y1, y0: bit;
);
end;

architecture verhalten of multiplexer i
    signal a3, a2, a1, a0: in bit;
    signal b3, b2, b1, b0: in bit;
    signal s: in bit;
    signal y3, y2, y1, y0: in bit;
begin
    y3 <= b3 and a3;
    y2 <= b2 and a2;
    y1 <= b1 and a1;
    y0 <= b0 and a0;
end;