/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/old-cs-2-01/vhdl-2021-07-16/myfirst00002.vhdl

entity FourBitAnd is
port
(
    a3, a2, a1, a0: in bit;
    b3, b2, b1, b0: in bit;
    s: in bit;
    c3, c2, c1, c0: in bit;
);
end;

architecture verhalten of FourBitAnd is
    signal x3, x2, x1, x0: bit;
    signal y3, y2, y1, y0: bit;
    signal s: bit;
    signal z3, z2, z1, z0: bit;
begin
    x3 <= a3;
    x2 <= a2;
    x1 <= a1;
    x0 <= a0;
    
    y3 <= b3;
    y2 <= b2;
    y1 <= b1;
    y0 <= b0;

    z3 <= y3 and x3;
    z2 <= y2 and x2;
    z1 <= y1 and x1;
    z0 <= y0 and x0;
    
    c3 <= z3;
    c2 <= z2;
    c1 <= z1;
    c0 <= z0;
end verhalten;