/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/old-cs-2-01/vhdl-2021-07-16/HalfAdd.vhdl

entity HalfAdder is
port
(
    a: in bit;
    b: in bit;
    s: out bit;
    c: out bit
);
end;

architecture structural of HalfAdder is
    signal at, bt, st, ct: bit;
begin
    bt
    at <= a;
    bt <= a;
    st <= at xor bt;
    ct <= at and bt;
    s <= st;
    c <= ct;
end structural;