/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-12-08/automat0043.txt

	b a x	b a y
0	0 0 0	0 1 0
1	0 0 1	1 1 0
2	0 1 0	0 1 1
3	0 1 1	1 0 0
4	1 0 0	1 1 0
5	1 0 1	0 0 0
6	1 1 0	0 1 0
7	1 1 1	0 0 0


	b a x	b
0	0 0 0	0
1	0 0 1	1
2	0 1 0	0
3	0 1 1	1
4	1 0 0	1
5	1 0 1	0
6	1 1 0	0
7	1 1 1	0

	b a x	a
0	0 0 0	1
1	0 0 1	1
2	0 1 0	1
3	0 1 1	0
4	1 0 0	1
5	1 0 1	0
6	1 1 0	1
7	1 1 1	0

	b a x	y
0	0 0 0	0
1	0 0 1	0
2	0 1 0	1
3	0 1 1	0
4	1 0 0	0
5	1 0 1	0
6	1 1 0	0
7	1 1 1	0



	b a x	b
1	0 0 1	1
3	0 1 1	1
4	1 0 0	1

	b a x	a
0	0 0 0	1
1	0 0 1	1
2	0 1 0	1
4	1 0 0	1
6	1 1 0	1

	b a x	y
2	0 1 0	1



	b a x	b
Gruppe 1:
1	0 0 1	1
4	1 0 0	1
Gruppe 2:
3	0 1 1	1

1:3		0 - 1
4		1 0 0

bout <= (not b and x) or
			(b and not a and not x);


	b a x	a
Gruppe 0:
0	0 0 0	1
Gruppe 1:
1	0 0 1	1
2	0 1 0	1
4	1 0 0	1
Gruppe 2:
6	1 1 0	1

0:1		0 0 -
0:2		0 - 0
0:4		- 0 0
2:6		- 1 0
4:6		1 - 0

0:4		- 0 0
2:6		- 1 0
0:2		0 - 0
4:6		1 - 0
0:1		0 0 -

0:4:2:6		- - 0
0:2:4:6		- - 0
0:1			0 0 -

aout <= (not x) or (not b and not a);




	b a x	y
2	0 1 0	1


bout <= (not b and x) or
			(b and not a and not x);
aout <= (not x) or (not b and not a);
y <= (not b and a and not x);

library ieee;
use ieee.std_logic_1164.all;

entity meinausgangsschaltnetz0043 is
port
(
	a, b, x: in std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinausgangsschaltnetz0043 is
begin
	y <= (not b and a and not x);
end;


library ieee;
use ieee.std_logic_1164.all;

entity meinuebergangsschaltnetz0043 is
port
(
	a, b, x: in std_logic;
	aout, bout: out std_logic
);
end;

architecture verhalten of meinuebergangsschaltnetz0043 is
begin
	bout <= (not b and x) or
			(b and not a and not x);
	aout <= (not x) or (not b and not a);
end;

library ieee;
use ieee.std_logic_1164.all;

entity testbenchschaltnetze0043 is
port (
	aout, bout, y: out std_logic
);
end;


architecture verhalten of testbenchschaltnetze0043 is
	component meinausgangsschaltnetz0043
	port (
		a, b, x: in std_logic;
		y: out std_logic
	);
	end component;
	component meinuebergangsschaltnetz0043
	port (
		a, b, x: in std_logic;
		aout, bout: out std_logic;
	);
	end component;
	signal a, b, x:	std_logic
begin
	u: meinuebergangsschaltnetz0043 PORT MAP (a=>a, b=>b, x=>x, aout=>aout, bout=>bout);
	a: meinausgangsschaltnetz0043 PORT MAP (a=>a, b=>b, x=>x, y=>y);


	x <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;

	a <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;

	b <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;


end;

library ieee;
use ieee.std_logic_1164.all;

entity rslatch0043 is
port (
	r, s: in std_logic;
	q: out std_logic
);
end;

architecture verhalten of rslatch0043 is
	signal q1, q2: std_logic;
begin
	q1 <= (s nor q2);
	q2 <= (r nor q1);
	q <= q1;
end;

library ieee;
use ieee.std_logic_1164.all;

entity clkrslatch0043 is
port (
	r, s: in std_logic;
	q: out std_logic;
	c: in std_logic
);
end;

architecture verhalten of clkrslatch0043 is
	component rslatch0043
	port
	(
		r, s: in std_logic;
		q: out std_logic
	);
	end;
	signal r1, s1: std_logic;
begin
	rs: rslatch0043 PORT MAP (r=>r1, s=>s1, q=>q);
	r1 <= r and c;
	s2 <= s and c;
end;


library ieee;
use ieee.std_logic_1164.all;


entity dlatch is
port
(
	q: out std_logic;
	c, d: in std_logic
);
end;

architecture verhalten of dlatch is
	component clkrslatch0043
	port
	(
		r, s, c: in std_logic;
		q: out std_logic
	);
	end;
	signal d1, d2: std_logic;
begin
	clkrs: clkrslatch0043 PORT MAP (r=>d1, s=>d2, c=>c, q=>q);
	d1 <= d;
	d2 <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dmsff is
port
(
	q: out std_logic;
	d, c: in std_logic
);
end;

architecture verhalten of dmsff is
	component dlatch
	port
	(
		q: out std_logic;
		d, c: in std_logic
	);
	end;
	signal d1, d2: std_logic;
	signal c1, c2: std_logic;
	signal q1, q2: std_logic;
begin
	master: dlatch PORT MAP (d=>d1, c=>c1, q=>q1);
	slave: dlatch PORT MAP (d=>d2, c=>c2, q=>q2);

	c1 <= c;
	c2 <= not c;

	d1 <= d;
	d2 <= q1;

	q <= q2;
end;