/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-12-08/automat0043c.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity meinausgangsschaltnetz0043 is
port
(
	a, b, x: in std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinausgangsschaltnetz0043 is
begin
	y <= (not b and a and not x);
end;


library ieee;
use ieee.std_logic_1164.all;

entity meinuebergangsschaltnetz0043 is
port
(
	a, b, x: in std_logic;
	aout, bout: out std_logic
);
end;

architecture verhalten of meinuebergangsschaltnetz0043 is
begin
	--bout <= (not b and x) or
			-- (b and not a and not x);
	--aout <= (not x) or (not b and not a);

	bout <= b xor a;
    aout <= not a;
end;


library ieee;
use ieee.std_logic_1164.all;

entity rslatch0043 is
port (
	r, s: in std_logic;
	q: out std_logic
);
end;

architecture verhalten of rslatch0043 is
	signal q1, q2: std_logic;
begin
	q1 <= (s nor q2);
	q2 <= (r nor q1);
	q <= q1;
end;

library ieee;
use ieee.std_logic_1164.all;

entity clkrslatch0043 is
port (
	r, s: in std_logic;
	q: out std_logic;
	c: in std_logic
);
end;

architecture verhalten of clkrslatch0043 is
	component rslatch0043
	port
	(
		r, s: in std_logic;
		q: out std_logic
	);
	end component;
	signal r1, s1: std_logic;
begin
	rs: rslatch0043 PORT MAP (r=>r1, s=>s1, q=>q);
	r1 <= r and c;
	s1 <= s and c;
end;


library ieee;
use ieee.std_logic_1164.all;


entity dlatch is
port
(
	q: out std_logic;
	c, d: in std_logic
);
end;

architecture verhalten of dlatch is
	component clkrslatch0043
	port
	(
		r, s, c: in std_logic;
		q: out std_logic
	);
	end component;
	signal d1, d2: std_logic;
begin
	clkrs: clkrslatch0043 PORT MAP (r=>d1, s=>d2, c=>c, q=>q);
	d1 <= d;
	d2 <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dmsff is
port
(
	q: out std_logic;
	d, c: in std_logic
);
end;

architecture verhalten of dmsff is
	component dlatch
	port
	(
		q: out std_logic;
		d, c: in std_logic
	);
	end component;
	signal d1, d2: std_logic;
	signal c1, c2: std_logic;
	signal q1, q2: std_logic;
begin
	master: dlatch PORT MAP (d=>d1, c=>c1, q=>q1);
	slave: dlatch PORT MAP (d=>d2, c=>c2, q=>q2);

	c1 <= c;
	c2 <= not c;

	d1 <= d;
	d2 <= q1;

	q <= q2;
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0043schaltwerk is
port
(
    c: in std_logic;
    x: in std_logic;
    we: inout std_logic;
    y: out std_logic
);
end;

architecture verhalten of meinautomat0043schaltwerk is
    component dmsff
    port
    (
        d, c: in std_logic;
        q: out std_logic
    );
    end component;
	component meinausgangsschaltnetz0043 is
	port
	(
		a, b, x: in std_logic;
		y: out std_logic
	);
	end component;
	component meinuebergangsschaltnetz0043 is
	port
	(
		a, b, x: in std_logic;
		aout, bout: out std_logic
	);
	end component;

    signal v1, v2 : std_logic;
    signal w1, w2 : std_logic;
    signal p1, p2 : std_logic;
    signal w_1, w_2 : std_logic;
    signal v_1, v_2 : std_logic;
begin
    state1: dmsff PORT MAP (d=>w_1, c=>c, q=>v1);
    state2: dmsff PORT MAP (d=>w_2, c=>c, q=>v2);
    ausgang: meinausgangsschaltnetz0043 PORT MAP (b=>v_1, a=>v_2, x=>x, y=>y);
    uebergang: meinuebergangsschaltnetz0043 PORT MAP (b=>v_1, a=>v_2, bout=>w1, aout=>w2,x=>x);

    w_1 <= w1 when we='1' else '0';
    w_2 <= w2 when we='1' else '0';
    v_1 <= v1 when we='1' else '0';
    v_2 <= v2 when we='1' else '0';
end;

library ieee;
use ieee.std_logic_1164.all;

entity testbenchschaltwerk0043 is
port
(
    y: inout std_logic
);
end;

architecture verhalten of testbenchschaltwerk0043 is
    component meinautomat0043schaltwerk
    port (
        c: in std_logic;
        we: in std_logic;
        x: in std_logic;
        y: out std_logic
    );
    end component;
    signal c: std_logic;
    signal we: std_logic;
    signal x: std_logic;
begin
    sw: meinautomat0043schaltwerk PORT MAP (c=>c, we=>we, x=>x, y=>y);

	c <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;

	we <= '1' after 0 ns, '0' after 10 ns;
	x <= '0' after 0 ns, '1' after 20 ns;
end;