/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/fsm20240226/quine20240224.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity quine20240224 is
port (
    x3, x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture behaviour of quine20240224 is
begin
    y <= (not x3 and x0) or
            (x3 and x1) or
            (x3 and x2);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20240224testbench is
port (
    y: out std_logic
);
end;

architecture behaviour of quine20240224testbench is
    component quine20240224
    port (
        x3, x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
    signal x3, x2, x1, x0: std_logic;
begin
    q: quine20240224 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);