/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/old-cs-2-01/vhdl-2021-07-16/q/halfadder.vhdl

entity halfadder is
port (
    X: in bit;
    y: in bit;
    sum: out bit;
    cout: out bit
);
end halfadder;

architecture behavioural of halfadder is
begin
    sum <= x xor y;
    cout <= x and y;
end behavioural;