/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/old-cs-2-01/vhdl-2021-07-16/q/fulladder.vhdl

entity halfadder is
port (
    X: in bit;
    y: in bit;
    sum: out bit;
    cout: out bit
);
end halfadder;

architecture behavioural of halfadder is
begin
    sum <= x xor y;
    cout <= x and y;
end behavioural;
 



entity fulladder is
port (
    x : in bit;
    y : in bit;
    cin : in bit;
    sum : out bit;
    cout : out bit
);
end fulladder;


architecture structural of fulladder is
    signal s1, s2, s3: bit;
    component halfadder
    port 
    (
        x: in bit;
        y: in bit;
        sum: out bit;
        cout: out bit;
    );
    end component;
    begin
        u1 : halfadder port map (x, y, s1, s2);
        u2 : halfadder port map (s1, cin, sum, s3);
        cout <= s2 or s3;
end structural;