/media/sda-magnetic/david/Dok-15-2023-11-27/Dokumente-15-appended-2023-10-11/append-temporarly/2023-10-02.vhdl

entity schaltung1 is 
port
(
    a0, a1, a2, a3: in bit;
    b0, b1, b2, b3: in bit;
    c0, c1, c2, c3: out bit
);
end;

architecture behaviour of schaltung1 is 
begin 
    c0 <= a0 and b0;
    c1 <= a1 and b1;
    c2 <= a2 and b2;
    c3 <= a3 and b3;
end;