/media/sda-magnetic/david/Dok-15-2023-11-27/Dokumente-15-appended-2023-10-11/append-temporarly/2023-10-02c.vhdl

entity diegroesseregewinnt is 
port
(
    c: out bit_vector (3 downto 0);
    b: in bit_vector (3 downto 0);
    a: in bit_vector (3 downto 0)
);
end;

architecture behaviour of diegroesseregewinnt is 
begin 
    c <=    a when (a(3) > b(3)) else
            b when (a(3) < b(3)) else
            a when (a(3) = b(3)) and (a(2) > b(2)) else
            b when (a(3) = b(3)) and (a(2) < b(2)) else
            a when (a(3) = b(3)) and (a(2) = b(2)) and (a(1) > b(1)) else
            b when (a(3) = b(3)) and (a(2) = b(2)) and (a(1) < b(1)) else 
            a when (a(3) = b(3)) and (a(2) = b(2)) and (a(1) = b(1)) and (a(0) > b(0)) else
            b when (a(3) = b(3)) and (a(2) = b(2)) and (a(1) = b(1)) and (a(0) < b(0)) else 
            a when (a(3) = b(3)) and (a(2) = b(2)) and (a(1) = b(1)) and (a(0) = b(0));
end;