/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/cs-04/excersize/vhdl-2023-12-17/automat0050.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity meinuebergangsschaltnetz0050 is
port (
	b, a, x: in std_logic;
	bout, aout: out std_logic
);
end;

architecture verhalten of meinuebergangsschaltnetz0050 is
begin
	bout <= (not b and x) or
		(b and not a and not x);
	aout <= (a and x) or
			(b and x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinausgangsschaltnetz0050 is
port (
	a, b, x: in std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinausgangsschaltnetz0050 is
begin
	y <= (not a and x) or
			(a and not x) or
			(b and a);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinetestbench0050automat is
port (
	y: out std_logic;
	bout, aout: out std_logic
);
end;

architecture verhalten of meinetestbench0050automat is
	component meinuebergangsschaltnetz0050
	port (
		b, a, x: in std_logic;
		bout, aout: out std_logic
	);
	end component;
	component meinausgangsschaltnetz0050
	port(
		b, a, x: in std_logic;
		y: out std_logic
	);
	end component;
	signal b, a, x: std_logic;
begin
	sn1: meinausgangsschaltnetz0050 PORT MAP (b=>b, a=>a, x=>x, y=>y);
	sn2: meinuebergangsschaltnetz0050 PORT MAP (b=>b, a=>a, x=>x, bout=>bout, aout=>aout);










x <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;

a <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;

b <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;

end;