/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/cs-04/excersize/vhdl-2023-12-17/automat0050.txt

	b a x	b a y
0	0 0 0	0 0 0
1	0 0 1	1 0 1
2	0 1 0	0 0 1
3	0 1 1	1 1 0
4	1 0 0	1 0 0
5	1 0 1	0 1 1
6	1 1 0	0 0 1
7	1 1 1	0 1 1


	b a x	b
0	0 0 0	0
1	0 0 1	1
2	0 1 0	0
3	0 1 1	1
4	1 0 0	1
5	1 0 1	0
6	1 1 0	0
7	1 1 1	0

	b a x	a
0	0 0 0	0
1	0 0 1	0
2	0 1 0	0
3	0 1 1	1
4	1 0 0	0
5	1 0 1	1
6	1 1 0	0
7	1 1 1	1

	b a x	y
0	0 0 0	0
1	0 0 1	1
2	0 1 0	1
3	0 1 1	0
4	1 0 0	0
5	1 0 1	1
6	1 1 0	1
7	1 1 1	1


	b a x	b
1	0 0 1	1
3	0 1 1	1
4	1 0 0	1

	b a x	a
3	0 1 1	1
5	1 0 1	1
7	1 1 1	1

	b a x	y
1	0 0 1	1
2	0 1 0	1
5	1 0 1	1
6	1 1 0	1
7	1 1 1	1


	b a x	b
Gruppe 1:
1	0 0 1	1
4	1 0 0	1
Gruppe 2:
3	0 1 1	1


	b a x	a
Gruppe 2:
3	0 1 1	1
5	1 0 1	1
Gruppe 3:
7	1 1 1	1

	b a x	y
Gruppe 1:
1	0 0 1	1
2	0 1 0	1
Gruppe 2:
5	1 0 1	1
6	1 1 0	1
Gruppe 3:
7	1 1 1	1



	b a x	b
Gruppe 1:
1	0 0 1	1
4	1 0 0	1
Gruppe 2:
3	0 1 1	1


1:3		0 - 1
4		1 0 0

	bout <= (not b and x) or
		(b and not a and not x);
	bout <= not (
				(b or not x) and
				(not b or a or x)
			);


	b a x	a
Gruppe 2:
3	0 1 1	1
5	1 0 1	1
Gruppe 3:
7	1 1 1	1

3:7		- 1 1
5:7		1 - 1

	aout <= (a and x) or
			(b and x);
	aout <= not (
				(not a or not x) and
				(not b or not x)
			);

	b a x	y
Gruppe 1:
1	0 0 1	1
2	0 1 0	1
Gruppe 2:
5	1 0 1	1
6	1 1 0	1
Gruppe 3:
7	1 1 1	1

1:5			- 0 1
2:6			- 1 0
5:7			1 - 1
6:7			1 1 -

		1	2	5	6	7
1:5		*		*
2:6			*		*
5:7				*		*
6:7					*	*


		1	2	5	6	7
1:5		*		*
2:6			*		*
6:7					*	*

1:5			- 0 1
2:6			- 1 0
6:7			1 1 -

	y <= (not a and x) or
			(a and not x) or
			(b and a);
	y <= not (
			(a or not x) and
			(not a or x) and
			(not b or not a)
		);

bout <= (not b and x) or
		(b and not a and not x);
	aout <= (a and x) or
			(b and x);
	y <= (not a and x) or
			(a and not x) or
			(b and a);

library ieee;
use ieee.std_logic_1164.all;

entity meinuebergangsschaltnetz0050 is
port (
	b, a, x: in std_logic;
	bout, aout: out std_logic
);
end;

architecture verhalten of meinuebergangsschaltnetz0050 is
begin
	bout <= (not b and x) or
		(b and not a and not x);
	aout <= (a and x) or
			(b and x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinausgangsschaltnetz0050 is
port (
	a, b, x: in std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinausgangsschaltnetz0050 is
begin
	y <= (not a and x) or
			(a and not x) or
			(b and a);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinetestbench0050automat is
port (
	y: out std_logic;
	bout, aout: out std_logic
);
end;

architecture verhalten of meinetestbench0050automat is
	component meinuebergangsschaltnetz0050
	port (
		b, a, x: in std_logic;
		bout, aout: out std_logic
	);
	end component;
	component meinausgangsschaltnetz0050
	port(
		b, a, x: in std_logic;
		y: out std_logic
	);
	end component;
	signal b, a, x: std_logic;
begin
	sn1: meinausgangsschaltnetz0050 PORT MAP (b=>b, a=>a, x=>x, y=>y);
	sn2: meinuebergangsschaltnetz0050 PORT MAP (b=>b, a=>a, x=>x, bout=>bout, aout=>aout);