0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 0
0 0 0 0 0 1
3 0 0 1 1 1
4 0 1 0 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
13 1 1 0 1 1
Gruppe 0
0 0 0 0 0 1
Gruppe 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2
3 0 0 1 1 1
9 1 0 0 1 1
10 1 0 1 0 1
Gruppe 3
7 0 1 1 1 1
13 1 1 0 1 1
0;4 0 - 0 0
0:8 - 0 0 0
8;9 1 0 0 -
8;10 1 0 - 0
3;7 0 - 1 1
9;13 1 - 0 1
8;9 1 0 0 -
8;10 1 0 - 0
3;7 0 - 1 1
9;13 1 - 0 1
0;4 0 - 0 0
0:8 - 0 0 0
(x3 and not x2 and not x1) or
(x3 and not x2 and not x0) or
(not x3 and x1 and x0) or
(x3 and not x1 and x0) or
(not x3 and not x1 and not x0) or
(not x2 and not x1 and not x0)
entity mydevice is
port (
x3, x2, x1, x0: in bit;
y: out bit;
);
end;
architecture behaviour of mydevice is
begin
y <= (x3 and not x2 and not x1) or (x3 and not x2 and not x0) or (not x3 and x1 and x0) or (x3 and not x1 and x0) or (not x3 and not x1 and not x0) or (not x2 and not x1 and not x0);
end behaviour;
