add adc sub sbb mul div neg inc dec and or xor not lods lodsb lodsw lodsd stos stosb stosw stosd movs movsb movsw movsd jmp cmp call ret int iret je jne jg jng jge jnge jl jnl jle jnle ja jna jae jnae jb jnb jbe jnbe in out push pop Sockel 423 Sockel 478 Sockel 775 1156 1155 1151 1150 1200 Westmere (Clarkdale) Sandy Bridge Ivy Bridge Hasswell-DT Skylake-S Kaby Lake-S Comet Lake-S Coffee Lake-S Intel-Core-i3-530 Intel-Core-i3-540 Intel-Core-i3-550 Intel-Core-i3-560 Intel-Core-i3-21xx Intel-Core-i3-32xx Intel-Core-i3-41xx Intel-Core-i3-43xx Intel-Core-i3-60xx Intel-Core-i3-61xx Intel-Core-i3-63xx Intel-Core-i3-71xx Intel-Core-i3-73xx Intel-Core-i3-81xx Intel-Core-i3-83xx Intel-Core-i3-91xx Intel-Core-i3-93xx Intel-Core-i3-101xx Intel-Core-i3-103xx DDR-200 PC-1600 DDR-266 PC-2100 DDR-333 PC-2700 DDR-400 PC-3200 DDR2-... PC2-... DDR3-... PC3-... DDR4-... PC4-... DDR5-... PC5-... 8020 8021 8022 8035 8039 8040 8048 8049 8050 8648 8748 8749 8031 8032 8051 8052 8751 8752 add addc anl orl xrl da swap clr cpl inc dec rr rrc rl rlc mov lds ld ldd sts st std in out push pop lmp ISR - Interrupt-Service-Routine - Interrupt-Handler IRQ - Interrupt-Request PIC 8259A - Programmable Interrupt Controller 8259A Eingänge: IR0 .. IR7, an jedem Eingang hängt ein Gerät D0 .. D7 mit den acht niederwertigsten Leiterbahnen des Datenbus verbunden INT angeschlossen an INTR der CPU INTA von CPU und Controller verbunden VCC, GND D7 .. D0 IR7 .. IR0 CAS 0, CAS 1, CAS 2 A0 -WR -RD -CS -SP/EN -INTA INT PIT - Programmable Intervall Timer - 8253 VCC, GND D7 .. D0 A1, A0 -WR -RD -CS CLK 2, OUT 2, GATE 2 CLK 1, OUT 1, GATE 1 CLK 0, OUT 0, GATE 0 8257/8237 Programmierbarer DMA Baustein 8255 Programmierbarer Paralleler Ein- und Ausgabebaustein