mov lea xchg add addc sub sbb mul div neg inc dec lods, lodsb, lodsw, lodsd stos, stosb, stosw, stosd movs, movsb, movsw, movsd jmp cmp call ret loop int reti je jne jg jng jge jnge jl jnl jle jnle ja jna jae jnae jb jnb jbe jnbe jc jnc jz jnz in out push pop Sockel 423 Sockel 478 Sockel 775 1156 1155 1151 1150 1200 Westmere (Clarkdale) Sandy Bridge Ivy Bridge Hasswel-DT Skylake-S Kaby Lake-S Comet Lake-S Coffee Lake-S Intel-Core-i3-530 Intel-Core-i3-540 Intel-Core-i3-550 Intel-Core-i3-560 Intel-Core-i3-2100 Intel-Core-i3-3200 Intel-Core-i3-4100 Intel-Core-i3-4300 Intel-Core-i3-6000 Intel-Core-i3-6100 Intel-Core-i3-6300 Intel-Core-i3-7100 Intel-Core-i3-7300 Intel-Core-i3-8100 Intel-Core-i3-8300 Intel-Core-i3-9100 Intel-Core-i3-9300 Intel-Core-i3-10100 Intel-Core-i3-10300 8020 8021 8022 8035 8039 8040 8048 8049 8050 8031 8032 8051 8052 add addc anl orl xrl da swap clr cpl inc dec rl rlc rr rrc mov lds ld ldd sts st std in out push pop lmp IRQ = Interrupt-Request = Interrupt-Anforderung = Unterbrechungsanforderung ISR = Interrupt-Service-Routine = Interrupt-Handler = Prozedur zur Unterbrechungsbehandlung = Unterbrechungsroutine = Interrupt-Routine = Interrupt-Behandlungs-Programm = Interrupt-Behandlung PIC 8259 A (Programmable Interrupt Controller) 8 Eingänge: IR0 .. IR7 8 Ausgänge: D0 bis D7 INTR von CPU und Controller verbunden INTA ?? INTR ?? CAS 0, CAS 1, CAS2 VCC, GND -WR, -EN ...? 8255: Paralleler Ein und Ausgabebaustein 82...??? OUT 0, GATE 0, CLK 0 OUT 1, GATE 1, CLK 1 OUT 2, GATE 2, CLK 2 PIT Programmable ... Timer ?? PIO: Programmed IO - Memory Mapped IO - Port Mapped IO Port Mapped IO: - in - out - Intel IO-Bereich = E/A-Bereich IO-Ports DMA - Direct Memory Access - Single Word DMA - Multi Word DMA - Ultra DMA