Next: /media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/vhdl/hello.vhdl Up: vhdl - ttl - Previous: /media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/vhdl/0001.vhdl
entity multiplexer is
port
(
S: in bit;
a, b: in bit_vector (0 to 3);
y: out bit_vector (0 to 3);
);
architecture behaviour of multiplexer is
signal a, b, y: bit_vector (0 to 3);
begin
end behaviour;