0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 1
1 0 0 0 1 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
9 1 0 0 1 1
11 1 0 1 1 1
13 1 1 0 1 1
15 1 1 1 1 1
Gruppe 1:
1 0 0 0 1 1
4 0 1 0 0 1
Gruppe 2:
3 0 0 1 1 1
5 0 1 0 1 1
6 0 1 1 0 1
9 1 0 0 1 1
Gruppe 3:
7 0 1 1 1 1
11 1 0 1 1 1
13 1 1 0 1 1
Gruppe 4:
15 1 1 1 1 1
1:3 0 0 - 1
1:5 0 - 0 1
4:9 - 0 0 1
4:5 0 1 0 -
4:6 0 1 - 0
3:7 0 - 1 1
3:11 - 0 1 1
5:7 0 1 - 1
5:13 - 1 0 1
6:7 0 1 1 -
9:11 1 0 - 1
9:13 1 - 0 1
7:15 - 1 1 1
11:15 1 - 1 1
13:15 1 1 - 1
4:5 0 1 0 -
6:7 0 1 1 -
1:3 0 0 - 1
13:15 1 1 - 1
4:6 0 1 - 0
5:7 0 1 - 1
9:11 1 0 - 1
1:5 0 - 0 1
9:13 1 - 0 1
11:15 1 - 1 1
3:7 0 - 1 1
3:11 - 0 1 1
4:9 - 0 0 1
5:13 - 1 0 1
7:15 - 1 1 1
Gruppe 1:
4:5 0 1 0 -
Gruppe 2:
6:7 0 1 1 -
4:5:6:7 0 1 - -
Gruppe 1:
4:6 0 1 - 0
1:3 0 0 - 1
Gruppe 2:
5:7 0 1 - 1
9:11 1 0 - 1
Gruppe 3:
13:15 1 1 - 1
4:6:5:7 0 1 - -
1:3:9:11 - 0 - 1
5:7:13:15 - 1 - 1
9:11:13:15 1 - - 1
Gruppe 1:
1:5 0 - 0 1
Gruppe 2:
9:13 1 - 0 1
3:7 0 - 1 1
Gruppe 3:
11:15 1 - 1 1
1:5:9:13 - - 0 1
1:5:3:7 0 - - 1
9:13:11:!5 1 - - 1
3:7:11:15 - - 1 1
Gruppe 1:
4:9 - 0 0 1
Gruppe 2:
5:13 - 1 0 1
3:11 - 0 1 1
Gruppe 3:
7:15 - 1 1 1
4:9:5:13 - - 0 1
4:9:3:11 - 0 - 1
5:13:7:15 - 1 - 1
3:11:7:15 - - 1 1
4:5:6:7 0 1 - -
4:6:5:7 0 1 - -
1:3:9:11 - 0 - 1
5:7:13:15 - 1 - 1
9:11:13:15 1 - - 1
1:5:9:13 - - 0 1
1:5:3:7 0 - - 1
9:13:11:!5 1 - - 1
3:7:11:15 - - 1 1
4:9:5:13 - - 0 1
4:9:3:11 - 0 - 1
5:13:7:15 - 1 - 1
3:11:7:15 - - 1 1
4:5:6:7 0 1 - -
4:6:5:7 0 1 - -
1:3:9:11 - 0 - 1
4:9:3:11 - 0 - 1
5:7:13:15 - 1 - 1
5:13:15 - 1 - 1
9:11:13:15 1 - - 1
9:13:11:!5 1 - - 1
1:5:3:7 0 - - 1
3:7:11:15 - - 1 1
3:11:7:15 - - 1 1
4:9:5:13 - - 0 1
1:5:9:13 - - 0 1
4:5:6:7 0 1 - -
1:3:9:11 - 0 - 1
5:7:13:15 - 1 - 1
9:11:13:15 1 - - 1
3:7:11:15 - - 1 1
4:9:5:13 - - 0 1
3:7:11:15:1:9:5:13 - - - 1
4:5:6:7 0 1 - -
1 0 0 0 1 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
9 1 0 0 1 1
11 1 0 1 1 1
13 1 1 0 1 1
15 1 1 1 1 1
y <= (x0) or (not x3 and x2)
y <= not (not(x0) and (x3 or not x2))
library ieee;
use ieee.std_logic_1164.all;
entity quine20240317 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240317 is
begin
y <= (x0) or (not x3 and x2);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240317testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240317testbench is
component quine20240317
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240317 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);