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0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 1
0 0 0 0 0 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
12 1 1 0 0 1
13 1 1 0 1 1
15 1 1 1 1 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
9 1 0 0 1 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
13 1 1 0 1 1
Grupppe 4:
15 1 1 1 1 1
0:2 0 0 - 0
0:4 0 - 0 0
0:8 - 0 0 0
2:3 0 0 1 -
4:12 - 1 0 0
8:9 1 0 0 -
8:12 1 - 0 0
3:7 0 - 1 1
9:13 1 - 0 1
12:13 1 1 0 -
7:15 - 1 1 1
13:15 1 1 - 1
0:2 0 0 - 0
13:15 1 1 - 1
2:3 0 0 1 -
8:9 1 0 0 -
12:13 1 1 0 -
0:4 0 - 0 0
8:12 1 - 0 0
3:7 0 - 1 1
9:13 1 - 0 1
0:8 - 0 0 0
7:15 - 1 1 1
4:12 - 1 0 0
0:2 0 0 - 0
13:15 1 1 - 1
2:3 0 0 1 -
8:9 1 0 0 -
12:13 1 1 0 -
0:4 0 - 0 0
8:12 1 - 0 0
9:13 1 - 0 1
3:7 0 - 1 1
0:8 - 0 0 0
4:12 - 1 0 0
7:15 - 1 1 1
Gruppe 0:
0:2 0 0 - 0
Gruppe 3:
13:15 1 1 - 1
Gruppe 1:
2:3 0 0 1 -
8:9 1 0 0 -
Gruppe 2:
12:13 1 1 0 -
Gruppe 0:
0:4 0 - 0 0
Gruppe 1:
8:12 1 - 0 0
Gruppe 2:
9:13 1 - 0 1
3:7 0 - 1 1
Gruppe 0:
0:8 - 0 0 0
Gruppe 1:
4:12 - 1 0 0
Gruppe 3:
7:15 - 1 1 1
Gruppe 0:
0:2 0 0 - 0
Gruppe 3:
13:15 1 1 - 1
Gruppe 1:
2:3 0 0 1 -
8:9 1 0 0 -
Gruppe 2:
12:13 1 1 0 -
8:9:12:13 1 - 0 -
Gruppe 0:
0:4 0 - 0 0
Gruppe 1:
8:12 1 - 0 0
Gruppe 2:
9:13 1 - 0 1
3:7 0 - 1 1
0:4:8:12 - - 0 0
1:12:9:13 1 - 0 -
3:7 0 - 1 1
Gruppe 0:
0:8 - 0 0 0
Gruppe 1:
4:12 - 1 0 0
Gruppe 3:
7:15 - 1 1 1
0:8:4:12 - - 0 0
7:15 - 1 1 1
0:2 0 0 - 0
13:15 1 1 - 1
2:3 0 0 1 -
8:9:12:13 1 - 0 -
0:4:1:12 - - 0 0
1:12:9:13 1 - 0 -
3:7 0 - 1 1
0:8:4:12 - - 0 0
7:15 - 1 1 1
0:2 0 0 - 0
13:15 1 1 - 1
2:3 0 0 1 -
8:9:12:13 1 - 0 -
1:12:9:13 1 - 0 -
0:4:8:12 - - 0 0
0:8:4:12 - - 0 0
3:7 0 - 1 1
7:15 - 1 1 1
0:2 0 0 - 0
13:15 1 1 - 1
2:3 0 0 1 -
8:9:12:13 1 - 0 -
0:4:1:12 - - 0 0
3:7 0 - 1 1
7:15 - 1 1 1
0 2 3 4 7 8 9 12 13 15
0:2 * *
13:15 * *
2:3 * *
8:9:12:13 * * * *
0:4:8:12 * * * *
3:7 * *
7:15 * *
0 2 3 4 7 8 9 12 13 15
13:15 * *
2:3 * *
8:9:12:13 * * * *
0:4:8:12 * * * *
3:7 * *
13:15 1 1 - 1
2:3 0 0 1 -
8:9:12:13 1 - 0 -
0:4:1:12 - - 0 0
3:7 0 - 1 1
y <= (x3 and x2 and x0) or
(not x3 and not x2 and x1) or
(x3 and not x1) or
(not x1 and not x0) or
(not x3 and x1 and x0);
y <= not (
(not x3 or not x2 or not x0) and
(x3 or x2 or not x1) and
(not x3 or x1) and
(x1 or x0) and
(x3 or not x1 or not x0)
);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240313 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240313 is
begin
y <= (x3 and x2 and x0) or
(not x3 and not x2 and x1) or
(x3 and not x1) or
(not x1 and not x0) or
(not x3 and x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240313testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240313testbench is
component quine20240313
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240313 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);