/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl20240411/quine20240402.txt

 0 0 0 0 0    0
 1 0 0 0 1    1
 2 0 0 1 0    1
 3 0 0 1 1    1
 4 0 1 0 0    1
 5 0 1 0 1    0
 6 0 1 1 0    1
 7 0 1 1 1    0
 8 1 0 0 0    0
 9 1 0 0 1    1
10 1 0 1 0    0
11 1 0 1 1    1
12 1 1 0 0    1
13 1 1 0 1    0
14 1 1 1 0    0
15 1 1 1 1    0


 1 0 0 0 1    1
 2 0 0 1 0    1
 3 0 0 1 1    1
 4 0 1 0 0    1
 6 0 1 1 0    1
 9 1 0 0 1    1
11 1 0 1 1    1
12 1 1 0 0    1


Gruppe 1:
 1 0 0 0 1    1
 2 0 0 1 0    1
 4 0 1 0 0    1
Gruppe 2:
 3 0 0 1 1    1
 6 0 1 1 0    1
 9 1 0 0 1    1
12 1 1 0 0    1
Gruppe 3:
11 1 0 1 1    1

1:3         0 0 - 1
1:9         - 0 0 1
2:3         0 0 1 -
2:6         0 - 1 0
4:6         0 1 - 0
4:12        - 1 0 0
3:11        - 0 1 1
9:11        1 0 - 1



2:3         0 0 1 -
1:3         0 0 - 1
4:6         0 1 - 0
9:11        1 0 - 1
2:6         0 - 1 0
1:9         - 0 0 1
4:12        - 1 0 0
3:11        - 0 1 1


Gruppe 1:
2:3         0 0 1 -

Gruppe 1:
1:3         0 0 - 1
4:6         0 1 - 0
Gruppe 2:
9:11        1 0 - 1

Gruppe 1:
2:6         0 - 1 0

Gruppe 1:
1:9         - 0 0 1
4:12        - 1 0 0

Gruppe 2:
3:11        - 0 1 1



Gruppe 1:
2:3             0 0 1 -

Gruppe 1:
1:3         0 0 - 1
4:6             0 1 - 0
Gruppe 2:
9:11        1 0 - 1

1:3:9:11        - 0 - 1

Gruppe 1:
2:6             0 - 1 0

Gruppe 1:
1:9         - 0 0 1
4:12            - 1 0 0
Gruppe 2:
3:11        - 0 1 1

1:9:3:1         - 0 - 1
3:11            - 0 1 1




2:3             0 0 1 -
4:6             0 1 - 0
1:3:9:11        - 0 - 1
2:6             0 - 1 0
1:9:3:1         - 0 - 1
3:11            - 0 1 1
4:12            - 1 0 0


2:3             0 0 1 -
4:6             0 1 - 0
1:3:9:11        - 0 - 1
2:6             0 - 1 0
3:11            - 0 1 1
4:12            - 1 0 0


                1   2   3   4   6   9   11  12
2:3                 *   *
4:6                         *   *
1:3:9:11        *       *           *   *
2:6                 *           *
3:11                    *               *
4:12                        *               *

                1   2   3   4   6   9   11  12
2:3                 *   *
4:6                         *   *               p
1:3:9:11        *       *           *   *       p
2:6                 *           *
3:11                    *               *
4:12                        *               *   p


                1   2   3   4   6   9   11  12
2:3                 *   *
4:6                         *   *               p
1:3:9:11        *       *           *   *       p
4:12                        *               *   p

2:3             0 0 1 -
4:6             0 1 - 0
1:3:9:11        - 0 - 1
4:12            - 1 0 0


    y <= (  (not x3 and not x2 and x1) or
            (not x3 and x2 and not x0) or
            (not x2 and x0) or
            (x2 and not x1 and not x0));

    y <= (  (x3 or x2 or not x1) and
            (x3 or not x2 or x0) and
            (x2 and not x0) and
            (not x2 or x1 or x0);

library ieee;
use ieee.std_logic_1164.all;

entity quine20240402 is
port (
    x3, x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture behaviour of quine20240402 is
begin
    y <= (  (not x3 and not x2 and x1) or
            (not x3 and x2 and not x0) or
            (not x2 and x0) or
            (x2 and not x1 and not x0));
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20240402testbench is
port (
    y: out std_logic
);
end;

architecture behaviour of quine20240402testbench is
    component quine20240402
    port (
        x3, x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
    signal x3, x2, x1, x0: std_logic;
begin
    q: quine20240402 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);