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0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
6 0 1 1 0 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
11 1 0 1 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
6 0 1 1 0 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
11 1 0 1 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
1 0 0 0 1
2:6 0 - 1 0
2:10 - 0 1 0
4:6 0 1 - 0
4:12 - 1 0 0
8:10 1 0 - 0
8:12 1 - 0 0
6:7 0 1 1 -
6:14 - 1 1 0
10:11 1 0 1 -
10:14 1 - 1 0
12:!4 1 1 - 0
7:15 - 1 1 1
11:15 1 - 1 1
14:15 1 1 1 -
1 0 0 0 1
Gruppe 1:
8:12 1 - 0 0
2:6 0 - 1 0
Gruppe 2:
10:14 1 - 1 0
Gruppe 3:
11:15 1 - 1 1
Gruppe 2:
10:11 1 0 1 -
6:7 0 1 1 -
Gruppe 3:
14:15 1 1 1 -
Gruppe 1:
8:10 1 0 - 0
4:6 0 1 - 0
Gruppe 2:
12:!4 1 1 - 0
Gruppe 1:
4:12 - 1 0 0
2:10 - 0 1 0
Gruppe 2:
6:14 - 1 1 0
Gruppe 3:
7:15 - 1 1 1
1 0 0 0 1
Gruppe 1:
8:12 1 - 0 0
2:6 0 - 1 0
Gruppe 2:
10:14 1 - 1 0
Gruppe 3:
11:15 1 - 1 1
8:12:10:14 1 - - 0
2:6:10:14 - - 1 0
10:14:11:15 1 - 1 -
Gruppe 2:
10:11 1 0 1 -
6:7 0 1 1 -
Gruppe 3:
14:15 1 1 1 -
10:11:14:!5 1 - 1 -
6:7:14:15 - 1 1 -
Gruppe 1:
8:10 1 0 - 0
4:6 0 1 - 0
Gruppe 2:
12:!4 1 1 - 0
8:10:12:14 1 - - 0
4:6:12:14 - 1 - 0
Gruppe 1:
4:12 - 1 0 0
2:10 - 0 1 0
Gruppe 2:
6:14 - 1 1 0
Gruppe 3:
7:15 - 1 1 1
4:12:6:14 - 1 - 0
2:10:6:14 - - 1 0
6:14:7:15 - 1 1 -
1 0 0 0 1
8:12:10:14 1 - - 0
2:6:10:14 - - 1 0
10:14:11:15 1 - 1 -
10:11:14:!5 1 - 1 -
6:7:14:15 - 1 1 -
8:10:12:14 1 - - 0
4:6:12:14 - 1 - 0
4:12:6:14 - 1 - 0
2:10:6:14 - - 1 0
6:14:7:15 - 1 1 -
1 0 0 0 1
8:12:10:14 1 - - 0
8:10:12:14 1 - - 0
10:14:11:15 1 - 1 -
10:11:14:!5 1 - 1 -
6:7:14:15 - 1 1 -
6:14:7:15 - 1 1 -
4:6:12:14 - 1 - 0
4:12:6:14 - 1 - 0
2:10:6:14 - - 1 0
2:6:10:14 - - 1 0
1 0 0 0 1
8:12:10:14 1 - - 0
10:14:11:15 1 - 1 -
6:7:14:15 - 1 1 -
4:6:12:14 - 1 - 0
2:10:6:14 - - 1 0
1 2 4 6 7 8 10 11 12 14 15
1 *
8:12:10:14 * * * *
10:14:11:15 * * * *
6:7:14:15 * * * *
4:6:12:14 * * * *
2:10:6:14 * * * *
1 2 4 6 7 8 10 11 12 14 15
1 *
8:12:10:14 * * * * p
10:14:11:15 * * * * p
6:7:14:15 * * * * p
4:6:12:14 * * * * p
2:10:6:14 * * * * p
1 0 0 0 1
8:12:10:14 1 - - 0
10:14:11:15 1 - 1 -
6:7:14:15 - 1 1 -
4:6:12:14 - 1 - 0
2:10:6:14 - - 1 0
y <= (not x3 and not x2 and not x1 and x0) or
(x3 and not x0) or
(x3 and x1) or
(x2 and x1) or
(x2 and not x0) or
(x1 and not x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240331 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240331 is
begin
y <= (not x3 and not x2 and not x1 and x0) or
(x3 and not x0) or
(x3 and x1) or
(x2 and x1) or
(x2 and not x0) or
(x1 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240331testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240331testbench is
component quine20240331
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240331 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);