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0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 0
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
7 0 1 1 1 1
9 1 0 0 1 1
10 1 0 1 0 1
14 1 1 1 0 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
Gruppe 2:
3 0 0 1 1 1
9 1 0 0 1 1
10 1 0 1 0 1
Gruppe 3:
7 0 1 1 1 1
14 1 1 1 0 1
0:1 0 0 0 -
0:2 0 0 - 0
1:3 0 0 - 1
1:9 1 0 0 -
3:7 0 - 1 1
10:14 1 - 1 0
0:1 0 0 0 -
1:9 1 0 0 -
0:2 0 0 - 0
1:3 0 0 - 1
3:7 0 - 1 1
10:14 1 - 1 0
Gruppe 0:
0:2 0 0 - 0
Gruppe 1:
1:3 0 0 - 1
0:2:1:10 0 0 -
Gruppe 1:
1:9 1 0 0 -
Gruppe 0:
0:1 0 0 0 -
1:9:0:1 - 0 0 -
Gruppe 2:
3:7 0 - 1 1
10:14 1 - 1 0
0:2:1:10 0 0 - -
1:9:0:1 - 0 0 -
3:7 0 - 1 1
10:14 1 - 1 0
0 1 2 3 7 9 10 14
0:2:1:10 * * * *
1:9:0:1 * * *
3:7 * *
10:14 * *
Alle notwendig
0:2:1:10 0 0 - -
1:9:0:1 - 0 0 -
3:7 0 - 1 1
10:14 1 - 1 0
y <= (not x4 and not x3) or
(not x2 and not x1) or
(not x3 and x1 and x0) or
(x3 and x1 and not x0);
y <= (x2 or x0) and
(x2 or x1) and
(x3 or not x1 or not x0) and
(not x3 or not x1 or x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240303 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240303 is
begin
y <= (not x4 and not x3) or
(not x2 and not x1) or
(not x3 and x1 and x0) or
(x3 and x1 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240303testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240303testbench is
component quine20240303
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240303 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);