/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl20240303/quine20240302.txt

 0 0 0 0 0    0
 1 0 0 0 1    0
 2 0 0 1 0    0
 3 0 0 1 1    0
 4 0 1 0 0    0
 5 0 1 0 1    0
 6 0 1 1 0    0
 7 0 1 1 1    1
 8 1 0 0 0    0
 9 1 0 0 1    1
10 1 0 1 0    0
11 1 0 1 1    0
12 1 1 0 0    1
13 1 1 0 1    0
14 1 1 1 0    0
15 1 1 1 1    1


 7 0 1 1 1    1
 9 1 0 0 1    1
12 1 1 0 0    1
15 1 1 1 1    1


Gruppe 2:
 9 1 0 0 1    1
12 1 1 0 0    1
Gruppe 3:
 7 0 1 1 1    1
Gruppe 4:
15 1 1 1 1    1


9           1 0 0 1     1
12          1 1 0 0     1
7:15        - 1 1 1     1

    y <= (x3 and not x2 and not x1 and x0) or
            (x3 and x2 and not x1 and not x0) or
            (x2 and x1 and x0);
    y <= not (
            (not x3 or x2 or x1 or not x0) and
            (not x3 or not x2 or x1 or x0) and
            (not x3 or not x2 or not x1)
        );

library ieee;
use ieee.std_logic_1164.all;

entity quine20240302 is
port (
    x3, x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture behaviour of quine20240302 is
begin
    y <= (x3 and not x2 and not x1 and x0) or
            (x3 and x2 and not x1 and not x0) or
            (x2 and x1 and x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity quine20240302testbench is
port (
    y: out std_logic
);
end;

architecture behaviour of quine20240302testbench is
    component quine20240302
    port (
        x3, x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
    signal x3, x2, x1, x0: std_logic;
begin
    q: quine20240302 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);