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0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0
0 0 0 0 0 1
2 0 0 1 0 1
4 0 1 0 0 1
6 0 1 1 0 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
6 0 1 1 0 1
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
0:2 0 0 - 0
0:4 0 - 0 0
0:8 - 0 0 0
2:6 0 - 1 0
2:10 - 0 1 0
4:6 0 1 - 0
4:12 - 1 0 0
8:9 1 0 0 -
8:10 1 0 - 0
8:12 1 - 0 0
8:9 1 0 0 -
0:2 0 0 - 0
4:6 0 1 - 0
8:10 1 0 - 0
0:4 0 - 0 0
8:12 1 - 0 0
2:6 0 - 1 0
0:8 - 0 0 0
2:10 - 0 1 0
4:12 - 1 0 0
8:9 1 0 0 -
Gruppe 0:
0:2 0 0 - 0
Gruppe 1:
4:6 0 1 - 0
8:10 1 0 - 0
0:2:4:6 0 - - 0
0:2:8:10 - 0 - 0
Gruppe 0:
0:4 0 - 0 0
Gruppe 1:
8:12 1 - 0 0
2:6 0 - 1 0
0:4:8:12 - - 0 0
0:4:2:6 0 - - 0
Gruppe 0:
0:8 - 0 0 0
Gruppe 1:
2:10 - 0 1 0
4:12 - 1 0 0
0:8:2:10 - 0 - 0
0:8:4:12 - - 0 0
8:9 1 0 0 -
0:2:4:6 0 - - 0
0:2:8:10 - 0 - 0
0:4:8:12 - - 0 0
0:4:2:6 0 - - 0
0:8:2:10 - 0 - 0
0:8:4:12 - - 0 0
8:9 1 0 0 -
0:2:4:6 0 - - 0
0:4:2:6 0 - - 0
0:2:8:10 - 0 - 0
0:8:2:10 - 0 - 0
0:4:8:12 - - 0 0
0:8:4:12 - - 0 0
8:9 1 0 0 -
0:4:2:6 0 - - 0
0:8:2:10 - 0 - 0
0:8:4:12 - - 0 0
0 2 4 6 8 9 10 12
8:9 * *
0:4:2:6 * * * *
0:8:2:10 * * * *
0:8:4:12 * * * *
8:9 1 0 0 -
0:4:2:6 0 - - 0
0:8:2:10 - 0 - 0
0:8:4:12 - - 0 0
y <= (x3 and not x2 and not x1) or
(not x3 and not x0) or
(not x2 and not x0) or
(not x1 and not x0);
y <= not ((not x3 or x2 or x1) and
(x3 or x0) and
(x2 or x0) and
(x1 or x0));
library ieee;
use ieee.std_logic_1164.all;
entity quine20240228 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240228 is
begin
y <= (x3 and not x2 and not x1) or
(not x3 and not x0) or
(not x2 and not x0) or
(not x1 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240228testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240228testbench is
component quine20240228
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240228 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);