/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2024-01-16/ampel20240111_02.vhdl

-- eine Fussgaengerampel zeigt normalerweise auf rot
-- drueckt man den Knopfl, geht sie auf gruen
-- dort bleibt sie fuer drei Sekunden
-- und geht zurueck auf rot

-- z0+ = z0 AND NOT Knopf OR z2
-- z1+ = z0 AND KNOPF
-- z2+ = z1
-- farbe = z0 AND knopf OR z1 OR z2

library ieee;
use ieee.std_logic_1164.all;

entity ampel20240111 is
port (
    farbe: out std_logic;
    knopf: in std_logic;
    z2p, z1p, z0p: out std_logic;
    z2, z1, z0: in std_logic
);
end;

architecture verhalten of ampel20240111 is
begin
    z0p <= ((z0 and not knopf) or z2);
    z1p <= (z0 and knopf);
    z2p <= (z1);
    farbe <= (z0 and knopf) or z1 or z2;
end;

library ieee;
use ieee.std_logic_1164.all;

entity rslatch20240111 is
port (
    r, s: in std_logic;
    q: out std_logic
);
end;


architecture verhalten of rslatch20240111 is
    signal q1, q2: std_logic;
    signal init: std_logic;
begin
    init <= '0' after 0 ns, '1' after 1 ns;

    q1 <= '1' when (init='0') else
            (q2 nor s);
    q2 <= '0' when (init='1') else
            (q1 nor r);
    q <= q1;
end;

library ieee;
use ieee.std_logic_1164.all;

entity crslatch20240111 is
port (
    r, s: in std_logic;
    q: out std_logic;
    c: in std_logic
);
end;

architecture verhalten of crslatch20240111 is
    component rslatch20240111
    port (
        r, s: in std_logic;
        q: out std_logic
    );
    end component;
    signal r1, s1: std_logic;
begin
    rslatch: rslatch20240111 PORT MAP (r=>r1, s=>s1, q=>q);
    r1 <= r and c;
    s1 <= s and c;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dlatch20240111 is
port (
    d: in std_logic;
    q: out std_logic;
    c: in std_logic
);
end;

architecture verhalten of dlatch20240111 is
    component crslatch20240111
    port (
        r, s: in std_logic;
        q: out std_logic;
        c: in std_logic
    );
    end component;
    signal r1, s1: std_logic;
begin
    crslatch: crslatch20240111 PORT MAP (r=>r1, s=>s1, c=>c, q=>q);
    s1 <= d;
    r1 <= not d;
end;

library ieee;
use ieee.std_logic_1164.all;

entity dmsff20240111 is
port (
    d: in std_logic;
    q: out std_logic;
    c: in std_logic
);
end;

architecture verhalten of dmsff20240111 is
    component dlatch20240111
    port (
        d: in std_logic;
        q: out std_logic;
        c: in std_logic
    );
    end component;
    signal c1, c2: std_logic;
    signal qd12: std_logic;
begin
    c1 <= c;
    c2 <= not c;
    master: dlatch20240111 PORT MAP (d=>d, c=>c1, q=>qd12);
    slave: dlatch20240111 PORT MAP (d=>qd12, c=>c2, q=>q);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meineampelschaltung20240111unaercodiert is
port (
    knopf: inout std_logic;
    farbe: out std_logic;
    takt: inout std_logic
);
end;

architecture verhalten of meineampelschaltung20240111unaercodiert is
    component dmsff20240111
    port (
        d: in std_logic;
        q: out std_logic;
        c: in std_logic
    );
    end component;
    component ampel20240111
    port (
        farbe: out std_logic;
        knopf: in std_logic;
        z2p, z1p, z0p: out std_logic;
        z2, z1, z0: in std_logic
    );
    end component;
    signal z2p, z1p, z0p: std_logic;
    signal z2, z1, z0: std_logic;
begin
    z2speicher: dmsff20240111 PORT MAP (q=>z2p, d=>z2, c=>takt);
    z1speicher: dmsff20240111 PORT MAP (q=>z1p, d=>z1, c=>takt);
    z0speicher: dmsff20240111 PORT MAP (q=>z0p, d=>z0, c=>takt);
    ampelschaltnetz: ampel20240111  PORT MAP (z2p=>z2p, z1p=>z1p, z0p=>z0p, z2=>z2, z1=>z1, z0=>z0, knopf=>knopf, farbe=>farbe);


    z2 <= '0' after 0 ns;
    z1 <= '0' after 0 ns;
    z0 <= '1' after 0 ns;
    takt <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;


    knopf <= '0' after 0 ns, '1' after 20 ns, '0' after 30 ns;
end;