/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl20240110/automat2024_01_03.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat2024_01_03 is
port (
    z3, z2, z1, z0: in std_logic;
    x1, x0: in std_logic;
    z3s, z2s, z1s, z0s: out std_logic;
    y: out std_logic
);
end;

architecture verhalten of meinautomat2024_01_03 is
begin
    z0s <= (z0) and not x1 and not x0;
    z1s <= ((z1) and not x1 and not x0) or (z2 and (not x1 and x0)) or (z3 and not x1 and not x0);
    z2s <= (z0 and not x1 and x0) or (z2 and not x1 and not x0) or (z2 and x1 and not x0);
    z3s <= (z0 and x1 and not x0);
    y <= (z0 and x1 and not x0) or (z2 and not x1 and not x0);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat2024_01_03_testbench is
port (
    z3s, z2s, z1s, z0s: out std_logic;
    y: out std_logic
);
end;

architecture verhalten of meinautomat2024_01_03_testbench is
    component meinautomat2024_01_03
    port (
        z3, z2, z1, z0: in std_logic;
        x1, x0: in std_logic;
        z3s, z2s, z1s, z0s: out std_logic;
        y: out std_logic
    );
    end component;
    signal z3, z2, z1, z0: std_logic;
    signal x1, x0: std_logic;
begin
    sn: meinautomat2024_01_03 PORT MAP (z3=>z3, z2=>z2, z1=>z1, z0=>z0, x1=>x1, x0=>x0, y=>y, z3s=>z3s, z2s=>z2s, z1s=>z1s, z0s=>z0s );


    x0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;

    x1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;

    z0 <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;

    z1 <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;

    z2 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;

    z3 <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '0' after 40 ns, '0' after 50 ns, '0' after 60 ns, '0' after 70 ns, '1' after 80 ns, '1' after 90 ns, '1' after 100 ns, '1' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;

end;