/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-12-31/quine0061.txt

 0 0 0 0 0    1
 1 0 0 0 1    1
 2 0 0 1 0    0
 3 0 0 1 1    0
 4 0 1 0 0    0
 5 0 1 0 1    1
 6 0 1 1 0    0
 7 0 1 1 1    0
 8 1 0 0 0    0
 9 1 0 0 1    1
10 1 0 1 0    0
11 1 0 1 1    0
12 1 1 0 0    0
13 1 1 0 1    0
14 1 1 1 0    1
15 1 1 1 1    1


 0 0 0 0 0    1
 1 0 0 0 1    1
 5 0 1 0 1    1
 9 1 0 0 1    1
14 1 1 1 0    1
15 1 1 1 1    1


Gruppe 0:
 0 0 0 0 0    1
Gruppe 1:
 1 0 0 0 1    1
Gruppe 2:
 5 0 1 0 1    1
 9 1 0 0 1    1
Gruppe 3:
14 1 1 1 0    1
Gruppe 4:
15 1 1 1 1    1

0:1     0 0 0 -
1:5     0 - 0 1
1:9     - 0 0 1
14:15   1 1 1 -

            0   1   5   9   14  15
0:1         *   *
1:5             *   *
1:9             *       *
14:15                       *   *

    y <= (not x3 and not x2 and not x1) or
            (not x3 and not x1 and x0) or
            (not x2 and not x1 and x0) or
            (x3 and x2 and x1);
    y <= not (
            (x3 or x2 or x1) and
            (x3 or x1 or not x0) and
            (x3 or x1 or not x0) and
            (not x3 or not x2 or not x1)
        );

library ieee;
use ieee.std_logic_1164.all;

entity meinschaltnetz0061 is
port
(
    x3, x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture verhalten of meinschaltnetz0061 is
begin
    y <= (not x3 and not x2 and not x1) or
            (not x3 and not x1 and x0) or
            (not x2 and not x1 and x0) or
            (x3 and x2 and x1);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinschaltnetz0061testbench is
port (
    y: out std_logic
);
end;

architecture verhalten of meinschaltnetz0061testbench is
    component meinschaltnetz0061
    port (
        x3, x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
    signal x3, x2, x1, x0: std_logic;
begin
    sn: meinschaltnetz0061 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);