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0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
6 0 1 1 0 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
15 1 1 1 1 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
6 0 1 1 0 1
9 1 0 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 4:
15 1 1 1 1 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
9 1 0 0 1 1
6 0 1 1 0 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 4:
15 1 1 1 1 1
1:3 0 0 - 1
1:9 - 0 0 1
2:6 0 - 1 0
2:10 - 0 1 0
4:6 0 1 - 0
4:12 - 1 0 0
1:10 1 0 - 0
1:12 1 - 0 0
15 1 1 1 1
1:3 0 0 - 1
4:6 0 1 - 0
1:10 1 0 - 0
1:9 - 0 0 1
4:12 - 1 0 0
2:10 - 0 1 0
2:6 0 - 1 0
1:12 1 - 0 0
15 1 1 1 1
Gruppe 1:
1:3 0 0 - 1
4:6 0 1 - 0
1:10 1 0 - 0
Gruppe 1:
1:9 - 0 0 1
4:12 - 1 0 0
2:10 - 0 1 0
Gruppe 1:
2:6 0 - 1 0
1:12 1 - 0 0
15 1 1 1 1
1:3 0 0 - 1
4:6 0 1 - 0
1:10 1 0 - 0
1:9 - 0 0 1
4:12 - 1 0 0
2:10 - 0 1 0
2:6 0 - 1 0
1:12 1 - 0 0
15 1 1 1 1
1 2 3 4 6 9 10 12 15
1:3 * *
4:6 * *
1:10 * *
1:9 * *
4:12 * *
2:10 * *
2:6 * +
1:12 * *
15 *
1 2 3 4 6 9 10 12 15
1:3 * *
4:6 * *
1:9 * *
2:10 * *
15 *
1:3 0 0 - 1
4:6 0 1 - 0
1:9 - 0 0 1
2:10 - 0 1 0
15 1 1 1 1
y <= (not x3 and not x2 and x0) or
(not x3 and x2 and not x0) or
(not x2 and not x2 and x0) or
(not x2 and x1 and not x0) or
(x3 and x2 and x1 and x0);
y <= not (
(x3 or x2 or not x0) and
(x3 or not x2 or x0) and
(x2 or x2 or not x0) and
(x2 or not x1 or x0) or
(not x3 or not x2 or not x1 or not x0)
);
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0056 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0056 is
begin
y <= (not x3 and not x2 and x0) or
(not x3 and x2 and not x0) or
(not x2 and not x2 and x0) or
(not x2 and x1 and not x0) or
(x3 and x2 and x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0056testbench is
port (
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0056testbench is
componnent meinschaltnetz0056
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
signal x3, x2, x1, x0: std_logic;
begin
sn: meinschaltnetz0056 PORT MAP (X3=>X3, x2=>x2, x1=>x1, x0=>x0, y=>y);