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0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 1
1 0 0 0 1 1
2 0 0 1 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
15 1 1 1 1 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
Gruppe 2:
5 0 1 0 1 1
6 0 1 1 0 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
11 1 0 1 1 1
13 1 1 0 1 1
Gruppe 4:
15 1 1 1 1 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
Gruppe 2:
5 0 1 0 1 1
6 0 1 1 0 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
11 1 0 1 1 1
13 1 1 0 1 1
Gruppe 4:
15 1 1 1 1 1
1:5 0 - 0 1
2:6 0 - 1 0
2:10 - 0 1 0
5:7 0 1 - 1
5:13 - 1 0 1
6:7 0 1 1 -
10:11 1 0 1 -
12:13 1 1 0 -
7:15 - 1 1 1
11:15 1 - 1 1
13:!5 1 1 - 1
1:5 0 - 0 1
2:6 0 - 1 0
11:15 1 - 1 1
5:7 0 1 - 1
13:!5 1 1 - 1
2:10 - 0 1 0
5:13 - 1 0 1
7:15 - 1 1 1
6:7 0 1 1 -
10:11 1 0 1 -
12:13 1 1 0 -
Gruppe 1:
1:5 0 - 0 1
2:6 0 - 1 0
Gruppe 3:
11:15 1 - 1 1
Gruppe 2:
5:7 0 1 - 1
Gruppe 3:
13:!5 1 1 - 1
Gruppe 1:
2:10 - 0 1 0
Gruppe 2:
5:13 - 1 0 1
Gruppe 3:
7:15 - 1 1 1
Gruppe 2:
6:7 0 1 1 -
10:11 1 0 1 -
12:13 1 1 0 -
1:5 0 - 0 1
2:6 0 - 1 0
11:15 1 - 1 1
Gruppe 2:
5:7 0 1 - 1
Gruppe 3:
13:!5 1 1 - 1
5:7:13:15 - 1 - 1
Gruppe 1:
2:10 - 0 1 0
Gruppe 2:
5:13 - 1 0 1
Gruppe 3:
7:15 - 1 1 1
5:13:7:15 - 1 - 1
Gruppe 2:
6:7 0 1 1 -
10:11 1 0 1 -
12:13 1 1 0 -
1:5 0 - 0 1
2:6 0 - 1 0
11:15 1 - 1 1
13:!5 1 1 - 1
5:7:13:15 - 1 - 1
2:10 - 0 1 0
5:13:7:15 - 1 - 1
6:7 0 1 1 -
10:11 1 0 1 -
12:13 1 1 0 -
1:5 0 - 0 1
2:6 0 - 1 0
11:15 1 - 1 1
13:!5 1 1 - 1
5:7:13:15 - 1 - 1
2:10 - 0 1 0
6:7 0 1 1 -
10:11 1 0 1 -
12:13 1 1 0 -
1 2 5 6 7 10 11 12 13 15
1:5 * *
2:6 * *
11:15 * *
13:15 * * * *
5:7:13:15
2:10 * *
6:7 * *
10:11 * *
12:13 * *
1 2 5 6 7 10 11 12 13 15
1:5 * *
2:6 * *
13:15 * * * *
5:7:13:15
10:11 * *
12:13 * *
1:5 0 - 0 1
2:6 0 - 1 0
13:!5 1 1 - 1
5:7:13:15 - 1 - 1
10:11 1 0 1 -
12:13 1 1 0 -
y <= (not x3 and not x1 and x0) or
(not x3 and x1 and not x0) or
(x3 and x2 and x0) or
(x2 and x0) or
(x3 and not x2 and x1) or
(x3 and x2 and not x1);
y <= not (
(x3 or x1 or not x0) and
(x3 or not x1 or x0) and
(not x3 or not x2 or not x0) and
(not x2 or not x0) and
(not x3 or x2 or not x1) and
(not x3 or not x2 or x0)
);
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0054 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0054 is
begin
y <= (not x3 and not x1 and x0) or
(not x3 and x1 and not x0) or
(x3 and x2 and x0) or
(x2 and x0) or
(x3 and not x2 and x1) or
(x3 and x2 and not x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity meinschaltnetz0054testbench is
port (
y: out std_logic
);
end;
architecture verhalten of meinschaltnetz0054testbench is
component meintschaltnetz0054
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
begin