/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-12-22/test.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity meinschaltnetz is
port (
    a, b: in std_logic;
    y: out std_logic
);
end;

architecture verhalten of meinschaltnetz is
begin
    y <= a and b;
end;

library ieee;
use ieee.std_logic_1164.all;

entity meingrosseschaltnetz is
port (
    y: out std_logic_vector (31 downto 0);
    b, a: in std_logic_vector (31 downto 0)
);
end;

architecture verhalten of meingrosseschaltnetz is
    component meinschaltnetz
    port (
        a, b: in std_logic;
        y: out std_logic
    );
    end component;
begin
    l1:
        for i in 0 to 31 generate
            sn: meinschaltnetz PORT MAP (b=>b(i), a=>a(i), y=>y(i));
        end generate;
end;