/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-12-22/ripplecarry.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
port (
    a, b, c: in std_logic;
    s, u: out std_logic
);
end;

architecture verhalten of fulladder is
begin
    s <= a xor b xor c;
    u <= (a and b) or ((a or b) and c);
end;

library ieee;
use ieee.std_logic_1164.all;

entity ripplecarryadder is
port (
    s: out std_logic_vector (31 downto 0);
    b, a: in std_logic_vector (31 downto 0)
);
end;

architecture verhalten of ripplecarryadder is
    component fulladder
    port (
        a, b, c: in std_logic;
        s, u: out std_logic
    );
    end component;
    signal c : std_logic_vector (31 downto 0);
    signal u : std_logic_vector (31 downto 0);
begin
    c(0) <= '0';
    add1: fulladder PORT MAP (c=>c(0),b=>b(0),a=>a(0),s=>s(0),u=>u(0));
    l1:
        for i in 1 to 31 generate
            sn: fulladder PORT MAP (c=>u(i-1),b=>b(i),a=>a(i),s=>s(i),u=>u(i));
        end generate;
end;

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
port (
    s: out std_logic_vector (31 downto 0)
);
end;

architecture verhalten of testbench is
    component ripplecarryadder
        port (
            s: out std_logic_vector (31 downto 0);
            b, a: in std_logic_vector (31 downto 0)
        );
    end component;
    signal b, a: std_logic_vector (31 downto 0);
begin
    sn: ripplecarryadder PORT MAP (b=>b, a=>a, s=>s);
    a (0) <= '1' after 0 ns, '0' after 1 ns , '1' after 2 ns, '0' after 3 ns;
    b (0) <= '1' after 0 ns;

    a (1) <= '1' after 0 ns, '0' after 2 ns;
    b (1) <= '0' after 0 ns;

    a (2) <= '0' after 0 ns;
    b (2) <= '1' after 0 ns;

    a (3) <= '1' after 0 ns;
    b (3) <= '1' after 0 ns;

end;