/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-12-22/automat0052.txt

	b a x	b a y
0	0 0 0	1 1 0
1	0 0 1	0 1 0
2	0 1 0	1 1 0
3	0 1 1	0 0 0
4	1 0 0	1 0 1
5	1 0 1	0 0 1
6	1 1 0	1 1 1
7	1 1 1	0 0 1


	b a x	b
0	0 0 0	1
1	0 0 1	0
2	0 1 0	1
3	0 1 1	0
4	1 0 0	1
5	1 0 1	0
6	1 1 0	1
7	1 1 1	0

	b a x	a
0	0 0 0	1
1	0 0 1	1
2	0 1 0	1
3	0 1 1	0
4	1 0 0	0
5	1 0 1	0
6	1 1 0	1
7	1 1 1	0

	b a x	y
0	0 0 0	0
1	0 0 1	0
2	0 1 0	0
3	0 1 1	0
4	1 0 0	1
5	1 0 1	1
6	1 1 0	1
7	1 1 1	1


	b a x	b
0	0 0 0	1
2	0 1 0	1
4	1 0 0	1
6	1 1 0	1

	b a x	a
0	0 0 0	1
1	0 0 1	1
2	0 1 0	1
6	1 1 0	1

	b a x	y
4	1 0 0	1
5	1 0 1	1
6	1 1 0	1
7	1 1 1	1



	b a x	b
Gruppe 0:
0	0 0 0	1
Gruppe 1:
2	0 1 0	1
4	1 0 0	1
Gruppe 2:
6	1 1 0	1

0:2		0 - 0
0:4		- 0 0
2:6		- 1 0
4:6		1 - 0

0:2		0 - 0
4:6		1 - 0
0:4		- 0 0
2:6		- 1 0

0:2:4:6		- - 0
0:4:2:6		- - 0


0:2:4:6		- - 0

	b <= (not x)
	b <= (not (x))



	b a x	a
Gruppe 0:
0	0 0 0	1
Gruppe 1:
1	0 0 1	1
2	0 1 0	1
Gruppe 2:
6	1 1 0	1

0:1			0 0 -
0:2			0 - 0
2:6			- 1 0

			0	1	2	6
0:1			*	*
0:2			*		*
2:6					*	*

			0	1	2	6
0:1			*	*
2:6					*	*

	a <= (not b and not a) or
			(a and not x);
	a <= not (
				(b or a) and
				(not a or x)
			);


	b a x	y
Gruppe 1:
4	1 0 0	1
Gruppe 2:
5	1 0 1	1
6	1 1 0	1
Gruppe 3:
7	1 1 1	1

4:5		1 0 -
4:6		1 - 0
5:7		1 - 1
6:7		1 1 -


4:5		1 0 -
6:7		1 1 -
4:6		1 - 0
5:7		1 - 1

4:5:6:7		1 - -
4:6:5:7		1 - -

	y <= b
	y <= not (not b)


	b <= (not x)
	a <= (not b and not a) or
			(a and not x);
	y <= b

library ieee;
use ieee.std_logic_1164.all;

entity meinuebergangsschaltnetz0052 is
port (
	bout, aout: out std_logic;
	b, a, x: in std_logic
);
end;

architecture verhalten meinuebergangsschaltnetz0052 is
begin
	bout <= (not x)
	aout <= (not b and not a) or
			(a and not x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinausgangsschaltnetz0052 is
port (
	y: out std_logic;
	b, a, x: in std_logic
);
end;

architecture verhalten of meinausgangsschaltnetz0052 is
begin
	y <= b
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0052testbench is
port (
	bout, aout: out std_logic;
	y: out std_logic
);
end;

architecture verhalten meinautomat0052testbench is
	component meinuebergangsschaltnetz0052
	port (
		bout, aout: out std_logic;
		b, a, x: in std_logic
	);
	end component;
	component meinausgangsschaltnetz0052
	port (
		y: out std_logic;
		b, a, x: in std_logic
	);
	end component;
	signal b, a, x: std_logic;
begin
	sn1: meinuebergangsschaltnetz0052 PORT MAP (b=>b, a=>a, x=>x, bout=>bout, aout=>aout);
	sn2: meinausgangsschaltnetz0052 PORT MAP (b=>b, a=>a, x=>x, y=>y);


	x <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	a <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	b <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;
end;