/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-12-19/quine0051.txt

 0 0 0 0 0    0
 1 0 0 0 1    1
 2 0 0 1 0    0
 3 0 0 1 1    0
 4 0 1 0 0    0
 5 0 1 0 1    0
 6 0 1 1 0    0
 7 0 1 1 1    0
 8 1 0 0 0    0
 9 1 0 0 1    1
10 1 0 1 0    1
11 1 0 1 1    0
12 1 1 0 0    1
13 1 1 0 1    1
14 1 1 1 0    1
15 1 1 1 1    1


 1 0 0 0 1    1
 9 1 0 0 1    1
10 1 0 1 0    1
12 1 1 0 0    1
13 1 1 0 1    1
14 1 1 1 0    1
15 1 1 1 1    1


Gruppe 1:
 1 0 0 0 1    1
Gruppe 2:
 9 1 0 0 1    1
10 1 0 1 0    1
12 1 1 0 0    1
Gruppe 3:
13 1 1 0 1    1
14 1 1 1 0    1
Gruppe 4:
15 1 1 1 1    1

1:9         - 0 0 1
10:14       1 - 1 0
12:13       1 1 0 -
12:14       1 1 - 0
13:15       1 1 - 1
14:15       1 1 1 -

1:9         - 0 0 1
10:14       1 - 1 0
12:13       1 1 0 -
14:15       1 1 1 -
12:14       1 1 - 0
13:15       1 1 - 1


1:9         - 0 0 1
10:14       1 - 1 0
Gruppe 2:
12:13       1 1 0 -
Gruppe 3:
14:15       1 1 1 -
Gruppe 2:
12:14       1 1 - 0
Gruppe 3:
13:15       1 1 - 1

12:13:14:15     1 1 - -
12:14:13:15     1 1 - -


1:9             - 0 0 1
10:14           1 - 1 0
12:13:14:15     1 1 - -
12:14:13:15     1 1 - -


1:9             - 0 0 1
10:14           1 - 1 0
12:14:13:15     1 1 - -

                1   9   10  12  13  14  15
1:9             *   *
10:14                   *           *
12:14:13:15                 *   *   *   *

    y <= (not x2 and not x1 and x0) or
            (x3 and x1 and not x0) or
            (x3 and x2);
    y <= not (
                (x3 or x1 or not x0) and
                (not x3 or not x1 or x0) and
                (not x3 or not x2)
            );







library ieee;
use ieee.std_logic_1164.all;

entity meinschaltnetz0051 is
port (
    x3, x2, x1, x0: in std_logic;
    y: out std_logic
);
end;

architecture verhalten of meinschaltnetz0051 is
begin
    y <= (not x2 and not x1 and x0) or
            (x3 and x1 and not x0) or
            (x3 and x2);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinschaltnetz0051testbench is
port (
    y: out std_logic
);
end;

architecture verhalten of meinschaltnetz0051testbench is
    component meinschaltnetz0051
    port (
        x3, x2, x1, x0: in std_logic;
        y: out std_logic
    );
    end component;
    signal x3, x2, x1, x0: std_logic;
begin
        sn: meinschaltnetz0051 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);