/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-12-19/automat0051.txt

	b a x	b a y
0	0 0 0	1 1 1
1	0 0 1	0 1 1
2	0 1 0	0 0 1
3	0 1 1	1 1 1
4	1 0 0	1 0 1
5	1 0 1	1 1 0
6	1 1 0	1 0 1
7	1 1 1	0 0 0


	b a x	b
0	0 0 0	1
1	0 0 1	0
2	0 1 0	0
3	0 1 1	1
4	1 0 0	1
5	1 0 1	1
6	1 1 0	1
7	1 1 1	0

	b a x	a
0	0 0 0	1
1	0 0 1	1
2	0 1 0	0
3	0 1 1	1
4	1 0 0	0
5	1 0 1	1
6	1 1 0	0
7	1 1 1	0

	b a x	y
0	0 0 0	1
1	0 0 1	1
2	0 1 0	1
3	0 1 1	1
4	1 0 0	1
5	1 0 1	0
6	1 1 0	1
7	1 1 1	0



	b a x	b
0	0 0 0	1
3	0 1 1	1
4	1 0 0	1
5	1 0 1	1
6	1 1 0	1

	b a x	a
0	0 0 0	1
1	0 0 1	1
3	0 1 1	1
5	1 0 1	1

	b a x	y
0	0 0 0	1
1	0 0 1	1
2	0 1 0	1
3	0 1 1	1
4	1 0 0	1
6	1 1 0	1


	b a x	b
Gruppe 0:
0	0 0 0	1
Gruppe 1:
4	1 0 0	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1
6	1 1 0	1

0:4		- 0 0
4:5		1 0 -
4:6		1 - 0
3		0 0 1

		0	4	5	6
0:4		*	*
4:5			*	*
4:6				*	*


		0	3	4	5	6
0:4		*		*
4:6					*	*
3			*

	b <= (not a and not x) or
			(b and not a) or
			(not b and not a and x);
	b <= not (
				(a or x) and
				(not b or x)
				(b or a or not x)
			);


	b a x	a
Gruppe 0:
0	0 0 0	1
Gruppe 1:
1	0 0 1	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1

0:1		0 0 -
1:3		0 - 1
1:5		- 0 1

		0	1	3	5
0:1		*	*
1:3			*	*
1:5			*		*

	a <= (not b and not a) or
			(not b and x) or
			(not a and x);
	a <= not (
			(b or a) and
			(b or not x) and
			(a or not x)
		);



	b a x	y
Gruppe 0:
0	0 0 0	1
Gruppe 1:
1	0 0 1	1
2	0 1 0	1
4	1 0 0	1
Gruppe 2:
3	0 1 1	1
6	1 1 0	1

0:1		0 0 -
0:2		0 - 0
0:4		- 0 0
1:3		0 - 1
2:3		0 1 -
2:6		- 1 0
4:6		1 - 0



0:4		- 0 0
2:6		- 1 0
1:3		0 - 1
4:6		1 - 0
0:2		0 - 0
2:3		0 1 -
0:1		0 0 -


Gruppe 0:
0:4		- 0 0
Gruppe 1:
2:6		- 1 0

Gruppe 0:
0:2		0 - 0
Gruppe 1:
1:3		0 - 1
4:6		1 - 0

Gruppe 0:
0:1		0 0 -
Gruppe 1:
2:3		0 1 -


Gruppe 0:
0:4		- 0 0
Gruppe 1:
2:6		- 1 0

0:4:2:6		- - 0

Gruppe 0:
0:2		0 - 0
Gruppe 1:
1:3		0 - 1
4:6		1 - 0

0:2:1:3		0 - -
0:2:4:6		- - 0

Gruppe 0:
0:1		0 0 -
Gruppe 1:
2:3		0 1 -

0:1:2:3		0 - -



0:4:2:6		- - 0
0:1:2:3		0 - -

y <= (not x or not b);

y <= (not (
			x and b
		))

	b <= (not a and not x) or
			(b and not x);
	a <= (not b and not a) or
			(not b and x) or
			(not a and x);
	y <= (not x or not b);

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0051uebergangsschaltnetz is
port (
	bout, aout: out std_logic;
	b, a, x: in std_logic
);
end;

architecture verhalten of meinautomat0051uebergangsschaltnetz is
begin
	bout <= (not a and not x) or
			(b and not x) or
			(not b and not a and x);
	aout <= (not b and not a) or
			(not b and x) or
			(not a and x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0051ausgangsschaltnetz is
port (
	y: out std_logic;
	b, a, x: in std_logic
);
end;

architecture verhalten of meinautomat0051ausgangsschaltnetz is
begin
	y <= (not x or not b);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinautomat0051testbench is
port (
	bout: out std_logic;
	aout: out std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinautomat0051testbench is
	component meinautomat0051uebergangsschaltnetz
	port (
		bout, aout: out std_logic;
		b, a, x: in std_logic
	);
	end component;
	component meinautomat0051ausgangsschaltnetz
	port (
		y: out std_logic;
		b, a, x: in std_logic
	);
	end component;
	signal b, a, x: std_logic;
begin
	sn1: meinautomat0051uebergangsschaltnetz PORT MAP (b=>b, a=>a, x=>x, bout=>bout, aout=>aout);
	sn2: meinautomat0051ausgangsschaltnetz PORT MAP (b=>b, a=>a, x=>x, y=>y);

	x <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	a <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	b <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;

end;