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/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-12-10/automat0046.txt 


	b a x	b a y
0	0 0 0	1 0 0
1	0 0 1	0 1 0
2	0 1 0	0 0 1
3	0 1 1	1 0 1
4	1 0 0	0 0 1
5	1 0 1	1 1 0
6	1 1 0	0 0 1
7	1 1 1	1 1 1


	b a x	b
0	0 0 0	1
1	0 0 1	0
2	0 1 0	0
3	0 1 1	1
4	1 0 0	0
5	1 0 1	1
6	1 1 0	0
7	1 1 1	1

	b a x	a
0	0 0 0	0
1	0 0 1	1
2	0 1 0	0
3	0 1 1	0
4	1 0 0	0
5	1 0 1	1
6	1 1 0	0
7	1 1 1	1

	b a x	y
0	0 0 0	0
1	0 0 1	0
2	0 1 0	1
3	0 1 1	1
4	1 0 0	1
5	1 0 1	0
6	1 1 0	1
7	1 1 1	1



	b a x	b
0	0 0 0	1
3	0 1 1	1
5	1 0 1	1
7	1 1 1	1

	b a x	a
1	0 0 1	1
5	1 0 1	1
7	1 1 1	1

	b a x	y
2	0 1 0	1
3	0 1 1	1
4	1 0 0	1
6	1 1 0	1
7	1 1 1	1


	b a x	b
Gruppe 0:
0	0 0 0	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1
Gruppe 3:
7	1 1 1	1


0	0 0 0
3:7	- 1 1
5:7	1 - 1

	b <= (not b and not a and not x) or
		(a and x) or
		(b and x);
	b <= not (
			(b or a or x) and
			(not a or not x) and
			(not b or not x)
		);

	b a x	a
1	0 0 1	1
5	1 0 1	1
7	1 1 1	1

1:5		- 0 1
5:7		1 - 1

	a <= (not a and x) or
			(b and x);
	a <= not (
			(a or not x) and
			(not or not x)
		);

	b a x	y
Gruppe 1:
2	0 1 0	1
4	1 0 0	1
Gruppe 2:
3	0 1 1	1
6	1 1 0	1
Gruppe 3:
7	1 1 1	1

2:3		0 1 -
2:6	 	- 1 0
1:6		1 - 0
3:7		- 1 1
6:7		1 1 -

2:3		0 1 -
6:7		1 1 -
2:6	 	- 1 0
3:7		- 1 1
1:6		1 - 0

2:3:6:7		- 1 -
2:6:3:7		- 1 -
1:6			1 - 0

	y <= (a) or (b and not x);
	y <= (not (not a) and (not b or x));



	b <= (not b and not a and not x) or
		(a and x) or
		(b and x);
	a <= (not a and x) or
			(b and x);
	y <= (a) or (b and not x);


library ieee;
use ieee.std_logic_1164.all;

entity meinausgangsschaltnetz0046 is
port (
	a, b, x: in std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinausgangsschaltnetz0046 is
begin
	y <= (a) or (b and not x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinuebergangsschaltnetz0046 is
port (
	b, a, x: in std_logic;
	bout, aout: out std_logic
);
end;

architecture verhalten of meinuebergangsschaltnetz0046 is
begin
	bout <= (not b and not a and not x) or
		(a and x) or
		(b and x);
	aout <= (not a and x) or
			(b and x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity testbench0046 is
port (
	bout, aout: out std_logic;
	y: out std_logic
);
end;

architecture verhalten of testbench0046 is
	component meinuebergangsschaltnetz0046
	port (
		b, a, x: in std_logic;
		bout, aout: out std_logic
	);
	end component;
	component meinausgangsschaltnetz0046
	port (
		b, a, x: in std_logic;
		y: out std_logic
	);
	end component;
	signal b, a, x: std_logic;
begin
	ueber: meinuebergangsschaltnetz0046 PORT MAP (b=>b, a=>a, x=>x, bout=>bout, aout=>aout);
	ausgang: meinausgangsschaltnetz0046 PORT MAP (b=>b, a=>a, x=>x, y=>y);

	x <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;

	a <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns;

	b <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns;
end;