library ieee; use ieee.std_logic_1164.all; entity meinausgangsschaltnetz0043 is port ( a, b, x: in std_logic; y: out std_logic ); end; architecture verhalten of meinausgangsschaltnetz0043 is begin y <= (not b and a and not x); end; library ieee; use ieee.std_logic_1164.all; entity meinuebergangsschaltnetz0043 is port ( a, b, x: in std_logic; aout, bout: out std_logic ); end; architecture verhalten of meinuebergangsschaltnetz0043 is begin bout <= (not b and x) or (b and not a and not x); aout <= (not x) or (not b and not a); end; library ieee; use ieee.std_logic_1164.all; entity testbenchschaltnetze0043 is port ( aout, bout, y: out std_logic ); end; architecture verhalten of testbenchschaltnetze0043 is component meinausgangsschaltnetz0043 port ( a, b, x: in std_logic; y: out std_logic ); end component; component meinuebergangsschaltnetz0043 port ( a, b, x: in std_logic; aout, bout: out std_logic ); end component; signal a, b, x: std_logic; begin s1: meinuebergangsschaltnetz0043 PORT MAP (a=>a, b=>b, x=>x, aout=>aout, bout=>bout); s2: meinausgangsschaltnetz0043 PORT MAP (a=>a, b=>b, x=>x, y=>y); x <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns, '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns; a <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns; b <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '0' after 100 ns, '0' after 110 ns, '1' after 120 ns, '1' after 130 ns, '1' after 140 ns, '1' after 150 ns; end;