/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-12-01/rslatchb.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity rs_latch2 is
port
(
    q: out std_logic;
    r, s: in std_logic
);
end;

architecture verhalten of rs_latch2 is
    signal q1, q2: std_logic;
begin
    q1 <= (q2 nor s);
    q2 <= (q1 nor r);
    q <= q1;
end;