/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-12-01/automat0042.vhdl

library ieee;
use ieee.std_logic_1164.all;

entity ausgangsschaltnetz0042 is
port
(
	a, b, x: in std_logic;
	y: out std_logic
);
end;

architecture verhalten of ausgangsschaltnetz0042 is
begin
	y <= (b and not a and not x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity uebergangsschaltnetz0042 is
port
(
	a, b, x: in std_logic;
	aout, bout: out std_logic
);
end;

architecture verhalten of uebergangsschaltnetz0042 is
begin
	bout <= (not x) or
		(not b and a);
	aout <= (not a) or
		(b and x) or
		(not b and not x);
end;