/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-11-28/myregister0001.vhdl

entity my_rs_latch is
port
(
    r, s: inout bit;
    q1, q2: out bit
);
end;

architecture verhalten of my_rs_latch is
begin
    q1 = r nor q2;
    q2 = s nor q1;
end;