/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-11-28/automat0030.vhdl

entity meinautomat0028ausgangschaltnetz is
port
(
	a, b: in bit;
	x: in bit;
	y0, y1, y2: out bit
);
end;

entity meinautomat0028uebergangsschaltnetz is
port
(
	a, b: in bit;
	aout, bout: out bit;
	x: in bit
);
end;

architecture verhalten of meinautomat0028ausgangschaltnetz is
begin
    y0 <= b;
    y1 <= a;
    y2 <= (not b and not a) or (b and a);
end;

architecture verhalten of meinautomat0028uebergangsschaltnetz is
begin
    bout <= b xor a;
    aout <= not a;
end;

entity meinautomat0028rslatch is
port (
    q: out bit;
    r, s: in bit
);
end;

architecture verhalten of meinautomat0028rslatch is
    signal q1, q2 : bit;
begin
    q1 <= (r nor q2);
    q2 <= (s nor q1);

    q <= q1;
end;


entity meinautomat0028rslatchtaktgesteuert is
port (
    q: out bit;
    r, s, c: in bit
);
end;

architecture verhalten of meinautomat0028rslatchtaktgesteuert is
    component meinautomat0028rslatch
    port (
        q: out bit;
        r, s: in bit
    );
    end component;
    signal r1, s1: bit;
begin
    instanzrslatch: meinautomat0028rslatch PORT MAP (r=>r1, s=>s1, q=>q);
    r1 <= c and r;
    s1 <= c and s;
end;

entity meinautomat0028dlatch is
port
(
    q: out bit;
    d, c: in bit
);
end;

architecture verhalten of meinautomat0028dlatch is
    component meinautomat0028rslatchtaktgesteuert
    port
    (
        q: out bit;
        r, s, c: in bit
    );
    end component;
    signal r1, s1: bit;
begin
    instanzrslatchtaktgesteuert: meinautomat0028rslatchtaktgesteuert PORT MAP (r=>r1, s=>s1, q=>q, c=>c);
    r1 <= d;
    s1 <= not d;
end;

entity meinautomat0028dmasterslaveflipflop is
port
(
    q: out bit;
    d, c: in bit
);
end;

architecture verhalten of meinautomat0028dmasterslaveflipflop is
    component meinautomat0028dlatch is
    port (
        q: out bit;
        d, c: in bit
    );
    end component;
    signal c1, c2: bit;
    signal d1: bit;
begin
    master: meinautomat0028dlatch PORT MAP (q=>d1, d=>d, c=>c1);
    slave: meinautomat0028dlatch PORT MAP (q=>q, d=>d1, c=>c2);
    c1 <= c;
    c2 <= not c;
end;

entity meinautomat0028schaltwerk is
port
(
    c: in bit;
    x: in bit;
    y0, y1, y2: out bit
);
end;

architecture verhalten of meinautomat0028schaltwerk is
    component meinautomat0028dmasterslaveflipflop
    port
    (
        d, c: in bit;
        q: out bit
    );
    end component;
    component meinautomat0028ausgangschaltnetz
    port
    (
        a, b: inout bit;
        x: in bit;
        y0, y1, y2: out bit
    );
    end component;
    component meinautomat0028uebergangsschaltnetz
    port
    (
        aout, bout: out bit;
        a, b: in bit;
        x: in bit
    );
    end component;
    signal v1, v2 : bit;
    signal w1, w2 : bit;
    signal p1, p2 : bit;
begin
    state1: meinautomat0028dmasterslaveflipflop PORT MAP (d=>w1, c=>c, q=>v1);
    state2: meinautomat0028dmasterslaveflipflop PORT MAP (d=>w2, c=>c, q=>v2);
    ausgang: meinautomat0028ausgangschaltnetz PORT MAP (b=>v1, a=>v2, x=>x, y0=>y0, y1=>y1, y2=>y2);
    uebergang: meinautomat0028uebergangsschaltnetz PORT MAP (b=>v1, a=>v2, bout=>w1, aout=>w2,x=>x);
end;

entity testbench is
    port (
        c: inout bit;
        x: inout bit;
        y0, y1, y2: out bit
    );
end;

architecture verhalten of testbench is
    component meinautomat0028schaltwerk
    port (
        c: in bit;
        x: in bit;
        y0, y1, y2: out bit
    );
    end component;

    component meinautomat0028rslatch
    port (
        q: out bit;
        r, s: in bit
    );
    end component;
    signal s, r, q: bit;
begin
    schaltwerk: meinautomat0028schaltwerk PORT MAP (c=>c, x=>x, y0=>y0, y1=>y1, y2=>y2);
    --c <= '1' after 1 ns, '0' after 2 ns, '1' after 3 ns, '0' after 4 ns,'1' after 5 ns, '0' after 6 ns,'1' after 7 ns, '0' after 8 ns,'1' after 9 ns, '0' after 10 ns, '1' after 11 ns, '0' after 12 ns,'1' after 13 ns, '0' after 14 ns,'1' after 15 ns, '0' after 16 ns;
    rs: meinautomat0028rslatch PORT MAP (q=>q, r=>r, s=>s);
    r <= '0' after 0 ns, '1' after 1 ns, '1' after 2 ns;
    s <= '0' after 0 ns, '0' after 1 ns, '1' after 2 ns;

end;