/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/vhdl-2023-11-28/automat0028.vhdl

entity meinautomat0028ausgangschaltnetz is
port
(
	a, b: inout bit;
	x: in bit;
	y0, y1, y2: out bit
);
end;

entity meinautomat0028uebergangsschaltnetz is
port
(
	a, b: inout bit;
	x: in bit
);
end;

architecture verhalten of meinautomat0028ausgangschaltnetz is
begin
	y0 <= (not b and x) or
		(b and a);
	y1 <= (b and not a and not x);
	y2 <= (b and a and x);
end;

architecture verhalten of meinautomat0028uebergangsschaltnetz is
begin
	b <= (b and not a) or
		(b and x);
	a <= (not b and x) or
		(not a and not x) or
		(b and a and x);
end;

entity meinautomat0028rslatch is
port (
    q1, q2: inout bit;
    r, s: in bit
);
end;

architecture verhalten of meinautomat0028rslatch is
begin
    q1 <= ((not r) nor q2);
    q2 <= ((not s) nor q1);
end;


entity meinautomat0028rslatchtaktgesteuert is
port (
    q1, q2: inout bit;
    r, s, c: in bit
);
end;

architecture verhalten of meinautomat0028rslatchtaktgesteuert is
    component meinautomat0028rslatch
    port (
        q1, q2: inout bit;
        r, s: in bit
    );
    end component;
    signal r1, s1: bit;
begin
    instanzrslatch: meinautomat0028rslatch PORT MAP (r=>r1, s=>s1, q1=>q1, q2=>q2);
    r1 <= c and r;
    s1 <= c and s;
end;

entity meinautomat0028dlatch is
port
(
    q1, q2: inout bit;
    d, c: in bit
);
end;

architecture verhalten of meinautomat0028dlatch is
    component meinautomat0028rslatchtaktgesteuert
    port
    (
        q1, q2: inout bit;
        r, s, c: in bit
    );
    end component;
    signal r1, s1: bit;
begin
    instanzrslatchtaktgesteuert: meinautomat0028rslatchtaktgesteuert PORT MAP (r=>r1, s=>s1, q1=>q1, q2=>q2, c=>c);
    r1 <= d;
    s1 <= not d;
end;

entity meinautomat0028dmasterslaveflipflop is
port
(
    q1, q2: inout bit;
    d, c: in bit
);
end;

architecture verhalten of meinautomat0028dmasterslaveflipflop is
    component meinautomat0028dlatch is
    port (
        q1, q2: inout bit;
        d, c: in bit
    );
    end component;
    signal c1, c2: bit;
    signal d1: bit;
begin
    master: meinautomat0028dlatch PORT MAP (q1=>d1, q2=>q2, d=>d, c=>c1);
    slave: meinautomat0028dlatch PORT MAP (q1=>q1, q2=>q2, d=>d1, c=>c2);
    c1 <= c;
    c2 <= not c;
end;

entity meinautomat0028schaltwerk is
port
(
    c: in bit;
    x: in bit;
    y0, y1, y2: out bit
);
end;

architecture verhalten of meinautomat0028schaltwerk is
    component meinautomat0028dmasterslaveflipflop
    port
    (
        d, c: in bit;
        q1, q2: inout bit
    );
    end component;
    component meinautomat0028ausgangschaltnetz
    port
    (
        a, b: inout bit;
        x: in bit;
        y0, y1, y2: out bit
    );
    end component;
    component meinautomat0028uebergangsschaltnetz
    port
    (
        a, b: inout bit;
        x: in bit
    );
    end component;
    signal v1, v2 : bit;

begin
    state1: meinautomat0028dmasterslaveflipflop PORT MAP (d=>b, c=>c, q1=>v1);
    state2: meinautomat0028dmasterslaveflipflop PORT MAP (d=>a, c=>c, q1=>v2);
    ausgang: meinautomat0028ausgangschaltnetz PORT MAP (b=>v1, a=>v2, x=>x, y0=>y0, y1=>y1, y2=>y2);
    uebergang: meinautomat0028uebergangsschaltnetz PORT MAP (b=>v1, a=>v2, x=>x);

end;