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0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
0 0 0 0 0 1
1 0 0 0 1 1
3 0 0 1 1 1
7 0 1 1 1 1
9 1 0 0 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
1 0 0 0 1 1
Gruppe 2:
3 0 0 1 1 1
9 1 0 0 1 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
0:1 0 0 0 -
1:3 0 0 - 1
1:9 - 0 0 1
3:7 0 - 1 1
9:13 1 - 0 1
12:13 1 1 0 -
12:14 1 1 - 0
7:15 - 1 1 1
13:15 1 1 - 1
14:15 1 1 1 -
0:1 0 0 0 -
12:13 1 1 0 -
14:15 1 1 1 -
1:3 0 0 - 1
12:14 1 1 - 0
13:15 1 1 - 1
3:7 0 - 1 1
9:13 1 - 0 1
7:15 - 1 1 1
1:9 - 0 0 1
Gruppe 0:
0:1 0 0 0 -
Gruppe 2:
12:13 1 1 0 -
Gruppe 3:
14:15 1 1 1 -
Gruppe 1:
1:3 0 0 - 1
Gruppe 2:
12:14 1 1 - 0
Gruppe 3:
13:15 1 1 - 1
Gruppe 2:
3:7 0 - 1 1
9:13 1 - 0 1
Gruppe 3:
7:15 - 1 1 1
Gruppe 1:
1:9 - 0 0 1
Gruppe 0:
0:1 0 0 0 -
Gruppe 2:
12:13 1 1 0 -
Gruppe 3:
14:15 1 1 1 -
0:1 0 0 0 -
12:13:14:15 1 1 - -
Gruppe 1:
1:3 0 0 - 1
Gruppe 2:
12:14 1 1 - 0
Gruppe 3:
13:15 1 1 - 1
1:3 0 0 - 1
12:14:13:15 1 1 - -
Gruppe 2:
3:7 0 - 1 1
9:13 1 - 0 1
3:7 0 - 1 1
9:13 1 - 0 1
Gruppe 3:
7:15 - 1 1 1
Gruppe 1:
1:9 - 0 0 1
7:15 - 1 1 1
1:9 - 0 0 1
0:1 0 0 0 -
12:13:14:15 1 1 - -
1:3 0 0 - 1
3:7 0 - 1 1
9:13 1 - 0 1
7:15 - 1 1 1
1:9 - 0 0 1
0 1 3 7 9 12 13 14 15
0:1 * *
12:13:14:15 * * * *
1:3 * *
3:7 * *
9:13 * *
7:15 * *
1:9 * *
0 1 3 7 9 12 13 14 15
0:1 * *
12:13:14:15 * * * *
3:7 * *
9:13 * *
0:1 0 0 0 -
12:13:14:15 1 1 - -
3:7 0 - 1 1
9:13 1 - 0 1
y <= (not x3 and not x2 and not x1) or
(x3 and x2) or
(not x3 and x1 and x0) or
(x3 and not x1 and x0);
y <= not(
(x3 or x2 or x1) and
(not x3 or not x2) and
(x3 or not x1 or not x0) and
(not x3 or x1 or not x0));
library ieee;
use ieee.std_logic_1164.all;
entity quine20240218 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240218 is
begin
y <= (not x3 and not x2 and not x1) or
(x3 and x2) or
(not x3 and x1 and x0) or
(x3 and not x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240218testbench is
port (
x3, x2, x1, x0: inout std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240218testbench is
component quine20240218
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
begin
q: quine20240218 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);