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0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 0
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
10 1 0 1 0 1
11 1 0 1 1 1
14 1 1 1 0 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
8 1 0 0 0 1
Gruppe 2:
5 0 1 0 1 1
6 0 1 1 0 1
10 1 0 1 0 1
Gruppe 3:
7 0 1 1 1 1
11 1 0 1 1 1
14 1 1 1 0 1
0:1 0 0 0 -
0:2 0 0 - 0
0:8 - 0 0 0
1:5 0 - 0 1
2:6 0 - 1 0
2:10 - 0 1 0
8:10 1 0 - 0
5:7 0 1 - 1
6:7 0 1 1 -
6:14 - 1 1 0
10:11 1 0 1 -
10:14 1 - 1 0
0:1 0 0 0 -
10:11 1 0 1 -
6:7 0 1 1 -
0:2 0 0 - 0
8:10 1 0 - 0
5:7 0 1 - 1
1:5 0 - 0 1
2:6 0 - 1 0
10:14 1 - 1 0
0:8 - 0 0 0
2:10 - 0 1 0
6:14 - 1 1 0
Gruppe 0:
0:1 0 0 0 -
Gruppe 2:
10:11 1 0 1 -
6:7 0 1 1 -
Gruppe 0:
0:2 0 0 - 0
Gruppe 1:
8:10 1 0 - 0
Gruppe 2:
5:7 0 1 - 1
Gruppe 1:
1:5 0 - 0 1
2:6 0 - 1 0
Gruppe 2:
10:14 1 - 1 0
Gruppe 0:
0:8 - 0 0 0
Gruppe 1:
2:10 - 0 1 0
Gruppe 2:
6:14 - 1 1 0
0:1 0 0 0 -
10:11 1 0 1 -
6:7 0 1 1 -
Gruppe 0:
0:2 0 0 - 0
Gruppe 1:
8:10 1 0 - 0
Gruppe 2:
5:7 0 1 - 1
0:2:8:10 - 0 - 0
5:7 0 1 - 1
Gruppe 1:
1:5 0 - 0 1
2:6 0 - 1 0
Gruppe 2:
10:14 1 - 1 0
1:5: 0 - 0 1
2:6:10:14 - - 1 0
Gruppe 0:
0:8 - 0 0 0
Gruppe 1:
2:10 - 0 1 0
Gruppe 2:
6:14 - 1 1 0
0:8:2:10 - 0 - 0
2:10:6:14 - - 1 0
0:1 0 0 0 -
10:11 1 0 1 -
6:7 0 1 1 -
0:2:8:10 - 0 - 0
5:7 0 1 - 1
1:5: 0 - 0 1
2:6:10:14 - - 1 0
0:8:2:10 - 0 - 0
2:10:6:14 - - 1 0
0:1 0 0 0 -
10:11 1 0 1 -
6:7 0 1 1 -
0:2:8:10 - 0 - 0
0:8:2:10 - 0 - 0
5:7 0 1 - 1
1:5: 0 - 0 1
2:6:10:14 - - 1 0
2:10:6:14 - - 1 0
0:1 0 0 0 -
10:11 1 0 1 -
6:7 0 1 1 -
0:2:8:10 - 0 - 0
5:7 0 1 - 1
1:5: 0 - 0 1
2:10:6:14 - - 1 0
0 1 2 5 6 7 8 10 11 14
0:1 * *
10:11 * *
6:7 * *
0:2:8:10 * * * *
5:7 * *
1:5: * *
2:10:6:14 * * * *
0 1 2 5 6 7 8 10 11 14
10:11 * *
0:2:8:10 * * * *
5:7 * *
1:5: * *
2:10:6:14 * * * *
10:11 1 0 1 -
0:2:8:10 - 0 - 0
5:7 0 1 - 1
1:5: 0 - 0 1
2:10:6:14 - - 1 0
y <= (x3 and not x2 and x1) or
(not x2 and not x0) or
(not x3 and x2 and x0) or
(not x3 and not x1 and x0) or
(x1 and not x0);
y <= not (
(not x3 or x2 or not x1) and
(x2 or x0) and
(x3 or not x2 or not x0) and
(x3 or x1 or not x0) and
(not x1 or x0)
);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240216 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240216 is
begin
y <= (x3 and not x2 and x1) or
(not x2 and not x0) or
(not x3 and x2 and x0) or
(not x3 and not x1 and x0) or
(x1 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240216testbench is
port (
x3, x2, x1, x0: inout std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240216testbench is
component quine20240216
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
begin
q: quine20240216 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);