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0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
1 0 0 0 1 1
3 0 0 1 1 1
5 0 1 0 1 1
7 0 1 1 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 1:
1 0 0 0 1 1
Gruppe 2:
3 0 0 1 1 1
5 0 1 0 1 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
11 1 0 1 1 1
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
1:3 0 0 - 1
1:5 0 - 0 1
3:7 0 - 1 1
3:11 - 0 1 1
5:7 0 1 - 1
5:13 - 1 0 1
10:11 1 0 1 -
10:14 1 - 1 0
12:13 1 1 0 -
12:14 1 1 - 0
7:15 - 1 1 1
11:15 1 - 1 1
13:15 1 1 - 1
14:15 1 1 1 -
5:13 - 1 0 1
7:15 - 1 1 1
3:11 - 0 1 1
1:5 0 - 0 1
3:7 0 - 1 1
10:14 1 - 1 0
11:15 1 - 1 1
1:3 0 0 - 1
5:7 0 1 - 1
12:14 1 1 - 0
13:15 1 1 - 1
10:11 1 0 1 -
12:13 1 1 0 -
14:15 1 1 1 -
Gruppe 2:
5:13 - 1 0 1
3:11 - 0 1 1
Gruppe 3:
7:15 - 1 1 1
5:13:7:15 - 1 - 1
3:11:7:15 - - 1 1
Gruppe 1:
1:5 0 - 0 1
Gruppe 2:
3:7 0 - 1 1
10:14 1 - 1 0
Gruppe 3
11:15 1 - 1 1
1:5:3:7 0 - - 1
3:7:11:15 - - 1 1
10:14:11:15 1 - 1 -
Gruppe 1:
1:3 0 0 - 1
Gruppe 2:
5:7 0 1 - 1
12:14 1 1 - 0
Gruppe 3:
13:15 1 1 - 1
1:3:5:7 0 - - 1
5:7:13:15 - 1 - 1
12:14:13:15 1 1 - -
10:11 1 0 1 -
12:13 1 1 0 -
14:15 1 1 1 -
10:11:14:15 1 - 1 -
12:13:14:15 1 1 - -
5:13:7:15 - 1 - 1
3:11:7:15 - - 1 1
1:5:3:7 0 - - 1
3:7:11:15 - - 1 1
10:14:11:15 1 - 1 -
1:3:5:7 0 - - 1
5:7:13:15 - 1 - 1
12:14:13:15 1 1 - -
10:11:14:15 1 - 1 -
12:13:14:15 1 1 - -
5:13:7:15 - 1 - 1
5:7:13:15 - 1 - 1
3:11:7:15 - - 1 1
3:7:11:15 - - 1 1
1:5:3:7 0 - - 1
1:3:5:7 0 - - 1
10:14:11:15 1 - 1 -
10:11:14:15 1 - 1 -
12:14:13:15 1 1 - -
12:13:14:15 1 1 - -
5:13:7:15 - 1 - 1
5:7:13:15 - 1 - 1
3:11:7:15 - - 1 1
3:7:11:15 - - 1 1
1:5:3:7 0 - - 1
1:3:5:7 0 - - 1
10:14:11:15 1 - 1 -
10:11:14:15 1 - 1 -
12:14:13:15 1 1 - -
12:13:14:15 1 1 - -
5:13:7:15 - 1 - 1
3:11:7:15 - - 1 1
1:5:3:7 0 - - 1
10:14:11:15 1 - 1 -
12:14:13:15 1 1 - -
1 3 5 7 10 11 12 13 14 15
5:13:7:15 * * * *
3:11:7:15 * * * *
1:5:3:7 * * * *
10:14:11:15 * * * *
12:14:13:15 * * * *
1 3 5 7 10 11 12 13 14 15
1:5:3:7 * * * *
10:14:11:15 * * * *
12:14:13:15 * * * *
1:5:3:7 0 - - 1
10:14:11:15 1 - 1 -
12:14:13:15 1 1 - -
y <= (not x3 and x0) or
(x3 and x1) or
(x3 and x2);
y <= (x3 or not x0) and
(not x3 or not x1) and
(not x3 or not x2);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240224 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240224 is
begin
y <= (not x3 and x0) or
(x3 and x1) or
(x3 and x2);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240224testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240224testbench is
component quine20240224
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240224 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);