0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 1
2 0 0 1 0 1
3 0 0 1 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 1
13 1 1 0 1 1
15 1 1 1 1 1
Gruppe 1:
2 0 0 1 0 1
Gruppe 2:
3 0 0 1 1 1
10 1 0 1 0 1
12 1 1 0 0 1
Gruppe 3:
11 1 0 1 1 1
13 1 1 0 1 1
Gruppe 4:
15 1 1 1 1 1
2:3 0 0 1 -
2:10 - 0 1 0
3:11 - 0 1 1
10:11 1 0 1 -
12:13 1 1 0 -
11:15 1 - 1 1
13:15 1 1 - 1
2:10 - 0 1 0
3:11 - 0 1 1
11:15 1 - 1 1
13:15 1 1 - 1
2:3 0 0 1 -
10:11 1 0 1 -
12:13 1 1 0 -
2:10 - 0 1 0
3:11 - 0 1 1
2:10:3:11 - 0 1 -
11:15 1 - 1 1
13:15 1 1 - 1
2:3 0 0 1 -
10:11 1 0 1 -
2:3:10:11 - 0 1 -
12:13 1 1 0 -
11:15 1 - 1 1
13:15 1 1 - 1
2:3:10:11 - 0 1 -
12:13 1 1 0 -
2 3 10 11 12 13 15
11:15 * *
13:15 * *
2:3:10:11 * * * *
12:13 * *
2 3 10 11 12 13 15
13:15 * *
2:3:10:11 * * * *
12:13 * *
13:15 1 1 - 1
2:3:10:11 - 0 1 -
12:13 1 1 0 -
y <= (x3 and x2 and x0) or
(not x2 and x1) or
(x3 and x2 and not x1);
y <= not (
(not x3 or not x2 or not x0) and
(x2 or not x1) and
(not x3 or not x2 or x1)
);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240222 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240222 is
begin
y <= (x3 and x2 and x0) or
(not x2 and x1) or
(x3 and x2 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240222testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240222testbench is
component quine20240222
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240222 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
