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0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
0 0 0 0 0 1
1 0 0 0 1 1
5 0 1 0 1 1
6 0 1 1 0 1
8 1 0 0 0 1
9 1 0 0 1 1
11 1 0 1 1 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
1 0 0 0 1 1
8 1 0 0 0 1
Gruppe 2:
5 0 1 0 1 1
6 0 1 1 0 1
9 1 0 0 1 1
Gruppe 3:
11 1 0 1 1 1
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
0:1 0 0 0 -
0:8 - 0 0 0
1:5 0 - 0 1
1:9 - 0 0 1
8:9 1 0 0 -
5:13 - 1 0 1
6:14 - 1 1 0
9:11 1 0 - 1
9:13 1 - 0 1
11:15 1 - 1 1
13:15 1 1 - 1
14:15 1 1 1 -
0:1 0 0 0 -
8:9 1 0 0 -
14:15 1 1 1 -
9:11 1 0 - 1
13:15 1 1 - 1
1:5 0 - 0 1
9:13 1 - 0 1
11:15 1 - 1 1
0:8 - 0 0 0
1:9 - 0 0 1
5:13 - 1 0 1
6:14 - 1 1 0
Gruppe 0:
0:1 0 0 0 -
Gruppe 1:
8:9 1 0 0 -
Gruppe 3:
14:15 1 1 1 -
Gruppe 2:
9:11 1 0 - 1
Gruppe 3:
13:15 1 1 - 1
Gruppe 1:
1:5 0 - 0 1
Gruppe 2:
9:13 1 - 0 1
Gruppe 3:
11:15 1 - 1 1
Gruppe 0:
0:8 - 0 0 0
Gruppe 1:
1:9 - 0 0 1
Gruppe 2:
5:13 - 1 0 1
6:14 - 1 1 0
Gruppe 0:
0:1 0 0 0 -
Gruppe 1:
8:9 1 0 0 -
Gruppe 3:
14:15 1 1 1 -
0:1:8:9 - 0 0 -
14:15 1 1 1 -
Gruppe 2:
9:11 1 0 - 1
Gruppe 3:
13:15 1 1 - 1
9:11:13:15 1 - - 1
Gruppe 1:
1:5 0 - 0 1
Gruppe 2:
9:13 1 - 0 1
Gruppe 3:
11:15 1 - 1 1
1:5:9:13 - - 0 1
9:13:11:!5 1 - - 1
Gruppe 0:
0:8 - 0 0 0
Gruppe 1:
1:9 - 0 0 1
Gruppe 2:
5:13 - 1 0 1
6:14 - 1 1 0
0:8:1:9 - 0 0 -
1:9:5:13 - - 0 1
0:1:8:9 - 0 0 -
14:15 1 1 1 -
9:11:13:15 1 - - 1
1:5:9:13 - - 0 1
9:13:11:!5 1 - - 1
0:8:1:9 - 0 0 -
1:9:5:13 - - 0 1
6:14 - 1 1 0
0:1:8:9 - 0 0 -
0:8:1:9 - 0 0 -
6:14 - 1 1 0
14:15 1 1 1 -
9:11:13:15 1 - - 1
9:13:11:!5 1 - - 1
1:5:9:13 - - 0 1
1:9:5:13 - - 0 1
0:1:8:9 - 0 0 -
6:14 - 1 1 0
14:15 1 1 1 -
9:11:13:15 1 - - 1
1:5:9:13 - - 0 1
0 1 5 6 8 9 11 13 14 15
0:1:8:9 * * * *
6:14 * *
14:15 * *
9:11:13:15 * * * *
1:5:9:13 * * * *
0 1 5 6 8 9 11 13 14 15
0:1:8:9 * * * *
6:14 * *
9:11:13:15 * * * *
1:5:9:13 * * * *
0:1:8:9 - 0 0 -
6:14 - 1 1 0
9:11:13:15 1 - - 1
1:5:9:13 - - 0 1
y <= (not x2 and not x1) or
(x2 and x1 and not x0) or
(x3 and x0) or
(not x1 and x0);
y <= not (
(x2 or x1) and
(not x2 or not x1 or x0) and
(not x3 or not x0) and
(x1 or not x0)
);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240215 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240215 is
begin
y <= (not x2 and not x1) or
(x2 and x1 and not x0) or
(x3 and x0) or
(not x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240215testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240215testbench is
component quine20240215
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240215 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);