/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/old-cs-2-03/fsm-2021-06-15/myadder3.vhdl

-- Also

entity FullAddrx is
port
(
  a : in bit;
  b : in bit;
  c : in bit;
  s : out bit;
  u : out bit
);
end;

architecture behvrx of FullAddrx is
begin
  abcdefg: process (a, b, c, u, s)
  begin 
    if (a = b) then
        u <= (a and b) or (b and c) or (a and c);
        s <= a xor b xor c;
    end if;
  end n;
end;