/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/old-cs-2-03/fsm-2021-06-15/2/fadder.vhdl

entity fladdr is
port 
(
    a: in bit;
    b: in bit;
    c0: in bit;
    s1: out bit;
    c1: out bit 
);
end;

architecture structure of fladdr is 
begin 
    s1 <= (a xor b xor c0);
    c1 <= (a and b) or (b and c0) or (a and c0);
end;